PCA9616 minimum pull-up resistance on SDA/SCL lines

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PCA9616 minimum pull-up resistance on SDA/SCL lines

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David_P
Contributor I

Hello NXP, 

We are running into some weird issues when integrating the PCA9616 into our application.

Our original design had 2.15K pull ups on the SDA/SCL lines, which was chosen to maintain good signal integrity on the clock waveforms. This resistance should be fine with the calculation for Rpmin found on page 50 of the UM10204 manual and output drive level rating of 3mA of the PCA9616 device running in fast or standard mode using a 3.3V single ended rail.

With this setup, we were not able to establish communication from our single ended master i2c through two PCA9616s to slave single ended i2c devices. The input waveforms to the master PCA9616 looked great but the differential output was not tracking the single ended input. 

We then breadboarded the circuit and tested different pullup resistances. Around a 3K and greater pullup, we noticed the current draw on the device reduce significantly (>30mA drop) and everything started working. After implementing the pullup value changes (5K for the prior 2.15K) into our full system resulted in everything working. Do you guys have an explanation for what we seeing? Is there a minimum pull up resistance for the SDA/SCL lines of this device?

Thanks, David

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