PCA9545 (correction: PCA9554) digital inputs damaged caused by long high rise times?

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PCA9545 (correction: PCA9554) digital inputs damaged caused by long high rise times?

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Contributor II

Correction of the chip number from Alois Lang (Author of this article): PCA9554

Text changed from PCA9545 to PCA9554 (January, 3th. 2020)

We use a PCA9554 I2C Port Extender Chip.
In our application, we use the 8 Digital I/O-lines as inputs (and defined by software).
Sometimes, we don't know when and why, one or more input's will be damaged or don't work correctly.
When this happens, it's not possible to read the status of these input pins, normally we see a high, when this input was damaged.
In front of all of these digital inputs we use at each pin a RC-low-pass-filter.
The designer of these board placed 1.1kOhm to +5V (when it goes to High) and 100 Ohm (when it goes to LOW) and 100nF to ground.

The rise and fall times of the Port-Pin’s at IO0 .. IO7 are very high, much too high, I guess ..

  • Rise time at a Port-pin IOx:: Tau = R * C  --> 1.1kOhm * 100nF = 110uS
  • Fall time at a Port-pin IOx: Tau = R * C  --> 100Ohm * 100nF = 10uS

 

It’s more unknown instead of a common knowledge in the electronics family, I guess, rise and fall times of CMOS input circuits mustn’t be higher than 100ns …1us max, otherwise a Schmitt-Trigger input have to be used.

But, normally, this max. rise and fall times of the Digital I/O-Pin’s can’t be found in a datasheet ….

 

Question to the application engineers of NXP and to the community:

Do you see a plausibility to destroy an input circuit by driving these inputs with this high rise times larger than 50 us?

--> Tau = 110us  --> from max. TTL-low level of 0.8V to the min TTL-high level of 2.0V -->  I would say, half of Tau is a correct value at the transition --> about 60us

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Contributor II

Correction of the information for the NXP chip:
It's a PCA 9554 in use and not a PCA 9545, I've mixed up the numbering, sorry for that.

I added a correction in the title and in the first blog.

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Contributor II

Dear Jozef,

many thanks for your replay, 

Circuit_2.png



I added the circuit part in which we have this unknown PCA9545 chip error.
This circuit detects, if a connector is connected to X12.x ( 8 identical connector detection circuits are linked to one PCA9545-chip)
At X12.1, we  make a bridge between pin P5 and P6 when a connector is connected, means, we pull the voltage from +5V (via pull up resistor R12) to GND, indicated by the red line at X12.1.

I wrote in my first blog, sometimes, we don't know when and why, one or more input's of this PCA9545 will be damaged or don't work correctly.

When this happens, it's not possible to read the status of these faulty input pins (sometimes one or more pins, never all pins).
We always read a high from the chip, when this inputs are damaged, but the connector pulls the input levels to low and we should read a low.

We are looking for the root cause of this failure, but we can’t solve it up to now.
We also discussed, if ESD could be the reason, but we think this isn't the case, in our protuction and EOL line, we are very carefully regarding ESD.

What is “8 Digital I/O-lines as inputs”? Are they 8 Digital I/O-lines as inputs” on system controller side or PCA9545 side (SC0-3, SD0-3) ?

8 Digital I/O-lines as inputs - means, we use the DIO-Interface as Inputs

 

Is “will be damaged” on system controller side or PCA9545 side?

See above

 

Is “will be damaged” soft damage (can be recovered after rest or power cycle PCA9545) or hard damage (can NOT be recovered after rest or power cycle PCA9545)?

Chip don't work anymore, we have to exchange the chip

 

I can’t image that “Rise time” or “Fall time” can cause hard damage of PCA9545’s SC0-3 and SD0-3 pins.

I refer to this Application note from TI: SCBA004D–July 1994–Revised September 2016 - Implications of slow or floating CMOS inputs.pdf
In this application note the author describes what could be happen, if rise and fall times are too slow

 

Please ask customer to give more clear explanations for their system testing configuration, procedure and failure mode.

We use 3 different testing stations in our chain of manucaturing.

We don't know, in which state these errors happens, we think it's not related to the production line, somtimes we get these errors also in the field.

Best Regards, Alois

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NXP TechSupport
NXP TechSupport

Dear Alois,

the application engineer has sent an update. Please measure the voltage levels on the input pins a send the results. Please see the description.

DESCRIPTION

Customer said “We always read a high from the chip, when this inputs are damaged, but the connector pulls the input levels to low and we should read a low”, please ask customer to use scope or multimeter to measure PCA9554 damage input pins (on PCA9554 pins) to see whether it is 0V or any other voltage level.

Best Regards,

Jozef

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Contributor II

Hello Jozef,

I measured at one board, I measured a voltage of 2.49V at two destroyed inputs.

All other inputs worked normal without any fail.

BR Alois

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Contributor II

More detailed - I measured 2 wrong boards:

At a High-Input, it's correctly high (3.5V in our case - 5V at the source, 100 R in series and a zener-diode to clamp it to 3.3V suppy voltage)

At a LOW-Input with our 100R resistor in series to GND, I measure a voltage of 2.49V in most cases, at one input I had 1.29V

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NXP TechSupport
NXP TechSupport

Hello Alois,

the application engineer has just sent me an answer. Please see the description.

DESCRIPTION

Customer said I measured a voltage of 2.49V at two destroyed inputs” and “At a LOW-Input with our 100R resistor in series to GND, I measure a voltage of 2.49V in most cases, at one input I had 1.29V”.

 

PCA9545 VIL Max = 0.3Vdd = 0.99V, so that it needs input voltage below 0.99V to be detected/reported as low level stably.

Please ask customer to short 100R resister in series to GND to see whether issue can be resolved.

Best Regards,

Jozef

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Contributor II

I checked the voltage at a non working (destroyed) input of this PCA9554:

With 100R resistor in series to GND, I measured about 2.45V

With a bridge across this 100R resistor (0R) I measure 0V at the input, so the level at the input this is ok and normal.

But the PCA9554 doesn't detect a LOW in this condition, it always see's a High at this input.

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NXP TechSupport
NXP TechSupport

Hello Alois,

the application engineer has sent an update. Please see the description.

DESCRIPTION

So if the voltage is 0V on input pins but PCA9554 reads in as high level, then please ask customer to send those damage parts through FA channel to test by ATE machine again to see whether the parts are damaged by EOS (Electrical Over-Stress).

Best Regards,

Jozef

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Contributor II

Dear Josef,

could you send the contact data of FA channel to me, I never used this service, to send some not working PCA9554-chips back to NXP for internal checks.

alois.lang@avl.com

Thank you very much

Best Regards, 

Alois

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NXP TechSupport
NXP TechSupport

Hello Alois,

 

I have asked the application engineer for more details regarding the FA Channel. Please check the https://www.nxp.com/support/sample-and-buy/distributor-network:DISTRIBUTORS#AUSTRIA for distributors in Austria. Please contact the one you have both the parts from. For app. eng. answer please see the description.

 

DESCRIPTION

 

Customer needs to submit FA (failure analysis) request and provide failure parts to the NXP local quality engineer (through NXP distributor or representative) to start with.

 

Best Regards,

Jozef

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Contributor II

Dear Jozef,

Thank you very much for your support, I'll collect a few non working PCA9554's and send it back for NXP internal inspection.

Best Regards, Alois

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NXP TechSupport
NXP TechSupport

Dear Alois

I want to ask you, whether you wouldn't mind if I close the case, or do you want to leave the case open for another seven days? 

Best Regards,

Jozef

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Contributor II

Hello Jozef,

please close this issue.

We couldn’t find a clear reason why this circuit design fails, so let’s see which answer we will get from NXP.

I’ll open a new case after this NXP clarifications if this is necessary.

Thank you very much,

BR Alois

Von: nxf58118 <admin@community.nxp.com>

Gesendet: Freitag, 24. Januar 2020 08:34

An: Lang, Alois AVL/AT <Alois.Lang@avl.com>

Betreff: Re: - Re: PCA9545 (correction: PCA9554) digital inputs damaged caused by long high rise times?

NXP Community <https://urldefense.proofpoint.com/v2/url?u=https-3A__community.freescale.com_resources_statics_1000_35400-2DNXP-2DCommunity-2DEmail-2Dbanner-2D600x75.jpg&d=DwMFaQ&c=fbaT_DgZBVToMmtoR86Pug&r=Ha7CmTo3-DLj1CwygACdsDLn52y7cIas46_PrmqRi4w&m=aw_hEflcIbNI3Fpl6jkU2fp_ehDsn4OGg8lQ0Q9NntI&s=BQz3aHgWiRQsodT8MQkYbwO2xWee-e2fllks5VnoE5s&e=>

Re: PCA9545 (correction: PCA9554) digital inputs damaged caused by long high rise times?

reply from Jozef Kozon<https://urldefense.proofpoint.com/v2/url?u=https-3A__community.nxp.com_people_nxf58118-3Fet-3Dwatches.email.thread&d=DwMFaQ&c=fbaT_DgZBVToMmtoR86Pug&r=Ha7CmTo3-DLj1CwygACdsDLn52y7cIas46_PrmqRi4w&m=aw_hEflcIbNI3Fpl6jkU2fp_ehDsn4OGg8lQ0Q9NntI&s=PYmOp2qpKDf-KhNkiybmz6F1oOuy5_H7lOUISbbkQ0M&e=> in Other NXP Products - View the full discussion<https://urldefense.proofpoint.com/v2/url?u=https-3A__community.nxp.com_message_1259893-3FcommentID-3D1259893-26et-3Dwatches.email.thread-23comment-2D1259893&d=DwMFaQ&c=fbaT_DgZBVToMmtoR86Pug&r=Ha7CmTo3-DLj1CwygACdsDLn52y7cIas46_PrmqRi4w&m=aw_hEflcIbNI3Fpl6jkU2fp_ehDsn4OGg8lQ0Q9NntI&s=jBczKirMkTITIX9vwUTRUibE9JGD9uiedAx0g3ZevJY&e=>

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NXP TechSupport
NXP TechSupport

Hello Alois,

sorry for a late reply. I was on Paid Time Off till yesterday. I have sent your measurements to the application engineer, hopefully he will answer me soon.

Best Regards,

Jozef

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NXP TechSupport
NXP TechSupport

Hello Alois,

I have asked the question an application engineer. He needs more details to the case. Can you provide answers to his questions? Please see the description.

DESCRIPTION

What is “8 Digital I/O-lines as inputs”? Are they 8 Digital I/O-lines as inputs” on system controller side or PCA9545 side (SC0-3, SD0-3) ?

 

Is “will be damaged” on system controller side or PCA9545 side?

 

Is “will be damaged” soft damage (can be recovered after rest or power cycle PCA9545) or hard damage (can NOT be recovered after rest or power cycle PCA9545)?

 

I can’t image that “Rise time” or “Fall time” can cause hard damage of PCA9545’s SC0-3 and SD0-3 pins.

 

Please ask customer to give more clear explanations for their system testing configuration, procedure and failure mode.

Best Regards,

Jozef

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