PCA85236A INTA/CLK pin status

[raja11]

Hi,

We are planning to use PCA85236AT/AJ device in our design. We see that the pin-7 is INTA/CLK. The output of this pin is controlled by INTAPM[1:0] register, which is set to 00 by default and selects CLK output mode. Also, the clock output is only available during VDD supply mode and is high impedance during battery mode. 

Based on this, I understand that INTA pin is high impedance when power is not supplied (and battery is connected). As soon as, VDD is applied the clock output will be available on this pin by default and the PCA85263A will pull this signal down at periodic interval based on clock frequency. Please confirm, if our understanding is correct.

Also, we are planning to use the INTA as watchdog reset output and hence we need to connect this signal to processor's reset input. As per our understanding, if this pin behaves as CLK by default, the board will keep getting reset as soon as IC is powered on. Is there a way to avoid the reset at power-up?

Regards,

Raja

[TomasVaverka]

Hi Raja,

First off, could you please confirm which part are you going to use? I suppose it is the PCF85263AT/AJ, right?

You are correct that the clock output is the default state of the INTA/CLK pin and is available only during VDD operation.

For your use case, I would recommend to use the TS pin configured to be the INTB output (TSPM[1:0] = 0b10) with watchdog function routed to it (WDIEB = 0b1).

Hope it helps.

Best regards,

Tomas

[raja11]

Hi Tomas,

Thanks for the response. Yes, the correct part number is PCF85263AT/AJ. We have ordered the samples of this part and built a small circuit to check the behaviour of INTA/CLK pin. We see that the pin is driven low continuously even when there is no power and only battery is connected. Just to give you an idea, the external pull-up on INTA and VDD are powered by two different 1.8V supply rails. In the starting, only INTA supply is up and VDD is absent. We see that this pin is still pulled low by PCF85236A device at regular intervals and asserts reset to the processor continuously. Do you have any idea on the same?

Also, regrading TS pin as recommended by you, we see that there is an internal pull-up on this device and we need an open-drain output. Hence, this pin can't be used.

Regards,

Raja