P3S0210BQ Oscillating

[smiller2]

We are evaluating the P3S0210BQ for a new design.   We need to mux together an I3C bus and a low voltage UART into a single downstream port.    When I attempt to send I3C through the MUX it starts oscillating.    Sinewave at about 50MHZ,  well over a volt in amplitude.    Oscillation continues until I pull the signal lines to GND.  Both SDA and SCL will oscillate.   I increased the series resistors, but did not help.   

 If I disable with the output enable, then the I3C connected to Port 1 can read the I3C temperature sensor on that port.    If I enable the output, then it can see neither the sensor on Port 1 or Port S.  

If I unplug the demo board, initialize the I3C bus to idle, and then hot plug the 5V to the demo board,  I can get both lines to a stable IDLE at 1.8V.   However, the first I3C transaction will start up the oscillation again. 

The I3C controller is inside an FPGA that is on a remote board.   There is probably over 24 inches of etch and a couple of connectors between the FPGA and the P3S0210BQ.    Is there a maximum trace spec on these interconnects?     Any app notes on choosing the series resistors or snubbers?    Thank you. 

[smiller2]

The schematic is too large and not very useful.   It is a Xilinx Artix FPGA driving multiple I2C/I3C buses.  At the FPGA there is a 1K pullup to the rail voltage which is adjustable.   Currently this voltage is at 1.8V.     I am attaching a scope capture of the oscillation starting.  Initially, the FPGA is holding SCL and SDA LOW.   On command, it releases them to IDLE which is both high.    As Port 1 ramps through a transition region, it starts to oscillate.       If I hold the OE pin low before releasing the SCL and SDA and then release it later, it will go to a stable IDLE.   However, the oscillation starts again when bus activity occurs.    On the demo board, all adjustable supplies are set to 3.3V.     I tried with pullup options, 1K, 2.2K and internal 10K.    

If I hold the OE pin low, then the FPGA can read the temperature sensor on Port 1 at 12.5MHZ.   So, the FPGA, its connections, and the voltage rail are OK onto the demo board.   The problem only shows up when I enable the translator. 

[smiller2]

I have a typo above. All the adjustable supplies on the demo board are set to 1.8V and not 3.3V. Right now we are trying to use the part simply as a mux. 1.8V in and 1.8V out.

[JozefKozon]

Dear Stephen,

could you please confirm the power supply pins voltage?

1. What voltages have you applied to the VCCR, VCCP1, VCCP2 and VCCS?

2. Please connect the P3S0210BQ directly to the FPGA and the sensor. Make the links as short as possible. 

3. Please use 30Ohm serial resistors on the lines as in our EVB. 

With Best Regards,

Jozef

[smiller2]

I took a new device and dead bugged it onto a piece of perf board.   All power pins were connected to 1.8V.     Series resistors were 47 ohms and pullups were 330 ohms.   Pullups again connected to 1.8V.    I see the same oscillation.   If I keep OE LOW, then I can drive I3C to the chip on Port 1 and the waveforms are clean.   If I allow OE to be pulled to 1.8V,  then it will start oscillating on the first or second transition.  

The board with the FPGA is already in the field and I cannot shorten the traces to the FPGA.   I don't think this part is suitable for systems with significant trace lengths.     The FPGA is probably about 4nS time of flight from this part.    I think the reflection back from the FPGA is causing the edge enhancement to turn this into an oscillator.  

[JozefKozon]

Dear Stephen,

I have sent a request for an advice on this issue. As soon as they will answer me, I will definitely reply to you.

Thank you for your patience. 

With Best Regards,

Jozef

[JozefKozon]

Dear Stephen,

I apologize for a late reply. There is still no answer from the application team. I have just sent them a reminder. As soon as they will answer me, I will definitely reply to you.

Thank you for your patience. 

With Best Regards,

Jozef

[JozefKozon]

Dear Stephen,

please see below an answer from the application engineer. The 24in length is too much load for the P3S0210BQ.

DESCRIPTION

We were able to simulate a similar case on our test bench with these conditions below and saw a round trip delay for the reflections of around 19ns:

24inch trace w/ 3pF/in and 7.5nH/in

Rseries = 50ohm

2 connectors added adding ~90pF

50ohm, 10pF load

19ns is too high. The on time of the one-shot block is ~10ns. If this kind of oscillations are to be avoided, the round trip delay should be less than 10ns. 24in trace already creates 8ns delay even without connectors and load.

This type of VLT with one-shot accelerator has this kind of limitation, unfortunately. There is no good way to overcome this without reducing the trace length.

With Best Regards,

Jozef

[JozefKozon]

Dear Stephen,

please share your schematic with voltage levels and part values. Please share the scopes of the SDA and SCL signals. 

For designing the I3C lines, please check the following documents attached. Very detailed information to the I3C and other documents can be found in this link. 

With Best Regads,

Jozef