P1022 local bus access issue

[rinkutakkar]

We are not able to access the local bus interface in P1022 . Following are the configuration settings:-

PMUXCR[eLBC_DIU] = 10   16-bit GPCM/ 28-bit Address

cfg_rom_loc[0:3] = 0110        On-chip boot ROM-SPI configuration

BR0 : E8001001

OR0 : F80000FF7

BR1 : FF800001

OR1 : FFFF8FF7

BR2 : FFDF0801

OR2: FFFF8FF7

BR3: FFEF8801

OR3: FFFF8FF7

Attached is the memory map as per our understanding.

Observations:

1. While trying to access any register within the specified range as per the base register and option register setting corresponding chip select signal is not asserted.

2. Processor does not boot up if we reconfigure the BR0 and OR0 register values in uboot file.

Kindly guide.

[alexander_yakov]

In addition to chipselect lines configuration in OR/BR registers, you should also properly configure Local access window registers. As long as you said chip select is not asserting, this may mean local access window is not configured to cover this address space, so the bus access is not going to local bus controller.

Have a great day,
Alexander
TIC

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[rinkutakkar]

Thanks a lot for your valuable comments.

There was actually a conflict with the LAW settings and address range defined in OR and BR registers.

For testing purpose,we are only configuring the chip select connected to CPLD that is CS3 , Following are the new configuration settings:-

1. Two LAWs are being assigned to local bus interface

    LAW1 : E8000000 - F8000000

    LAW2 : FFDF0000 - FFE00000

2.  BR3: FFDF8000

     OR3: FFE00000

But still there is no success, CS3 is not asserted when we try to access any location within the specified range.

Kindly guide about the possible causes for the same.

[alexander_yakov]

Your new config is incorrect - the value FFDF8000 is not a valid setting, it contains invalid value for port size PS=00 and also "valid" bit V is not set, which means this chip select line is inactive.

Please become familiar with P1022 Reference Manual, Sections 13.3.1 and 13.3.2

[rinkutakkar]

There was a typo in my previous reply. Please accept my apologies for the same.

I wrote the actual beginning and end addresses for CS3 instead of the base register and option register values.

BR3 : FFDF8801

OR3 : FFFF8FF7

Please comment.

[alexander_yakov]

I do not see anything incorrect in your OR3/BR3 settings. If you do not see CS3 assertions with these settings, that the problem is somewhere else. Please check, if there is no overlap in OR/BR register pairs and also in Local access windows.

[rinkutakkar]

The specified range for CS3 in OR and BR registers completely fall within the allocated LAW for local bus controller.

There is one thing i wanted to clarify as we have configured the processor for GPCM-16 (16-bit GPCM/ 28-bit Address) that is A0 - A27 lines of the address bus are mapped as the 4-31 bits of 32 bit address actually being accessed. Should it be a matter of concern? Will the LAW settings and OR, BR settings are also dependent on this mode of usage of local bus.

Please guide.

[alexander_yakov]

Thank you for confirmation that CS3 address range completely falls into local bus access window.

Please also check all local access windows, if they are not overlap. Reference Manual states "If two or more LAWs overlap, the lower numbered window takes precedence." (Section 2.4.1)

Different address pin multiplexing modes should not affect CS3 assertion, but CS3 itself is multifunction pin and may be configured for other function in some modes. For example, in "DIU and 8-bit NAND" mode CS3 pin acts a DIU pin. In mode "16-bit GPCM/ 28-bit Address" this pin acts as CS3, so I do not expect any issue here.

[rinkutakkar]

Thanks for your comments

There is one thing i would like to point out that we are booting the processor from SPI interface and there is no specification of any address range used by this interface in the LAW settings.The chip defines the default boot ROM address range to be 8 Mbytes at address 0x0_FF80_0000 to 0x0_FFFF_FFFF. Could there be a possibility of any conflict here. Please comment.

[alexander_yakov]

Yes, conflict is possible. You can verify this by moving your GPCM device to any other address location not used by other memory devices.