Hello diazmarin09,
Thanks for the confirmation that my schematic is correct.
- I've reffered to these tables and calculated the minimal resistance which is required on Bn and An. The sink current for 1 FPGA pin is 8mA. For my first design I interpolated roughly to a resistor of minimal 800 Ohm, thus chose to pick a little bigger resistor (1K). Calculating through the provided formula within the AN11127 document(https://www.nxp.com/docs/en/application-note/AN11127.pdf) I end up with a minimal resistor of:
(5.0-0.33)/8mA -3Ohm = 580,75 Ohm.
Not sure how much this will affect operation of the NVT2006PW.
The An pins have no pull-up resistors and are not pulled up to refA. There is a 1k resistor in series with the An pin to the encoder (has to be respected through datasheet encoder). But I don't see how that would result in not operating.
-So you're saying that it is normal to measure a 0.9V drop on the 200k resistor? This ends up in the fact that I dont have a 5V ref on RefB?? For me this is important, because the low voltage wont be accepted as a valid signal.
-I supply my board with a 5V line. This is translated to 3.3V by an LDO. On the 3.3V supply from the LDO there is a decoupling bank (in the image below). Through there the ref for the 3.3V is made. The 5V ref is directly linked to the 5V supply of the board (with the 200k res inbetween ofcourse).
Another image is included is the 1k serial resistance which I've spoken about. These lead to a header (to a different board with just the FPGA and decoupling).
As the current state is, is that I keep getting off reading and I'm considering the component could be broken due to bad soldering. Its being interchanged as we speak.
-On RefA I measured 3.3V steady.
-Passive voltage on An pins was 3.43V
-The 2MHz signal I provided on a pin was showing at the 3.3V side as expected.
-On RefB/EN I measured 4.08V and didn't see the clock signal coming trough on the expected Bn line.


**Update**
I've installed a new NVT2006PW,118 on my pcb and the CLK signal of 2 MHz I'm providing on the 3.3V side is converted of a 5V signal. So this works! Seems the old NVT2006PW,118 wasn't working.
Still though I see a different problem. The signal on the level shifter doesn't go back to GND.
On the 3.3V side i see it deviating from 3.3V high, 3V low.
On the 5V side I see the signal going from 5V high to 3.3V low.
Any idea how this is possible?
**Update 2** 13-12-2021
After stepwise measuring the system through I noticed that the CLK signal from the FPGA was fine untill the resistor R14 (FPGA side). On the level shifter side I noticed that the signal did not return back to GND, but from 3.3V to 3V. I desoldered the 1K R14 and placed a 0Ohm jumper instead. Now it seems to translate fine! 3.3 to GND and ~4.85V to 0.33V as specified in the datasheet.
Thought it would be nice to share my findings for other members aswell. Not precisely sure how this 1k resistor matters this much. But he sure was the problem.
Thanks for the help you're providing!
Dear regards,
Ramon Schonewille