Meaning of M in 'M2 memory' like 'Level' in L2 cache and M1 memory placement in SC3850 subsystem

[kanu__]

hi,

In the case of starcore 3850 core sub system , i can see M2 memory (configured from L2 cache)

I have some querries,

1) What is the meaning of 'M' in M2 memory usage like 'Level 2 ' in L2 cache

2) I can't see any M1 memory in the star core 3850 subsystem.

3) how M2 came without M1 in the SC3850 sub system?

Expecting your reply.

__Kanu

[J2MEJediMaster · Accepted solution]

1) You are correct. 'M' equals memory.

2) You do not see M1 memory because there is not any. There is a level-1 (L1) cache, but it cannot be addressed by a program, nor configured to act as accessible memory. It is cache memory that is strictly under the 3850's control.

3) As explained in 1), there is not any M1 memory. M2 memory is called such to help identify which memory level/cache level you are using.

---Tom

[kanu__]

Thanks. Good answer . Perfectly fine. 

Also i have one humble suggestions ,

1) Can you please answer my previous question in the below link 

https://community.freescale.com/thread/69053

Because i haven't got any replies to this question yet.

2) Can you explain me the MMU functions (protection + translation) feature in the SC 3850 architecture?

__Kanu

[barbara_johnson]

The MMU checks whether a program or data access matches the permissions defined in the MMU address and translation table (MATT). If not, an MMU exception is triggered. For example, if a specific memory range in M3 is defined in the MMU to be for program only, then a data access to this memory space will cause a MMU error exception. The goal of memory protection is to increase system reliabiltiy so memory cannot be accessed by tasks that are not supposed to be accessing it based on the MATT.

The MMU also performs virtual to physical address translation to allow users to write software without consideration of the physical location of the code in memory. The software is then simpler and modular since code is reolcatable by the MMU. For example if all cores are running the same task, the user does not have to write multiple code with different locations.

[kanu__]

The first point is fine.

But the second point regarding the address translation, Can you compare one system with no MMU and its draw backs and another one with MMU enabled? to justify your second point more clearly to me?

How can we manage/fill a MMU table for particular task ?

ie How a MMU table look like? any example?

and Who takes this MMU table and manages the task properties?(the linker?)

How a linker reads and associates the properties/entries in the MMU table ?

What is the concept of one to one in MMU(virtual to physical) ?

Why some cache algorithms is directly depending on the MMU mechanism?

Also is it possible to avoid the MMU mechanism by making the linker /loader logic more specifically?

__Kanu