I'm using the FPGA for writing a real-time camera data via RapidIO into the external DDR memory.
When the algorithm increases it processing usage, the FPGA's buffers get overflow.
I need to set the CLASS priority to prioritize RapidIO.
How can I do that?
Set C0PMR8 = C0PMR12 = 0x00003333 which will make data from/to HSSI the highest priority on CLASS.
Besides priority, set C0AWR8 = C0AWR12 = 7 for best performance.