MPC8641D as RC, what are LAWs, ATMUs, and BARs ?

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MPC8641D as RC, what are LAWs, ATMUs, and BARs ?

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Contributor I

I am working with the MPC8641D (to be used as an RC device) and have some newbie confusion surrounding PCI Express usage and LAWs, ATMUs and BARs.

 

I read that LAWs map a region of 36 bit local address space to target interface.  Does this mean they assign MPC8641 internal addresses to its internal 'peripherals’ (PCIe, RapidIO, etc etc) ?   These are addresses on the so called “platform bus” ... absolutely nothing to do with the LBC or external address bus.

 

What then do ATMUs do ?  I did see they “translate a 36 bit local address to an external address, or translate an external address to a 36 bit local address space”.   What does “external address” refer to here ?  

 

If LAWs and ATMUs are overlapping in some way, why are they both needed ?

 

I am getting all of this confused with ‘traditional’ PCI BARs, and am not sure who is who anymore. 

 

I "see" things more clearly through graphical/pictorial representations .. any idea where I could find any ?

 

Thank you

 

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5 Replies

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NXP Employee
NXP Employee

You can think of LAW's as part of the main system bus. They map addesses on this bus to peripherals. For example, you would have LAW's set up to map:
    Addresses 0 - 0x3FFF_FFFF to DDR
    0x4000_0000-0x4FFF_FFFF to PCI
    0x5000_0000 - 0x5FFF_FFFF to Local Bus
    0x6000_0000 - 0x7000_0000 to RapidIO
This is from the system's point of view (or system bus) so its not an address that the core see's - this is a physical address, past the MMU. Anytime the system bus see's this address it knows where to steer it to.

Let's say the MMU has address translation turned on & virtual address 0xcfff_fff3 maps to physical address 0x5fff_fff3. Using the abvove LAW's, once this transaction hits the ECM (system bus coherency module) it will be steered to the Local Bus. Then the local bus chip selects have to be set up to do something with this address. If ORx and BRx are set up to handle 0x5fff_fff3 (physical address again) then the transaction will result in a chip select assertion. Otherwise you'll get a LBC error of some sort.

ATMU's are similar to the PCI BAR's that you mentioned. These map from PCI (for example) space to the internal space of the chip. You have inbound and outbound windows to set up transactions on the ingress & egress of these peripherals. So, for example, one might set up an inbound window that translates a PCI address of 0x5000_0000 - 0x5fff_ffff to be translated into a chip address of 0x000_0000 to 0x0FFF_FFFF. These work in conjunction with LAW's. So, now if the PCI bus then saw a transaction of 0x5000_0004, the PCI controller would translate it to an address of 0x0000_0004 and put the transaction on the internal system bus. Since there's a LAW set up, (using the above LAW example) this would be steered towards DDR.

Outbound ATMU's work similarly. A CPU write to physical address 0x4000_00FF would be steered towards the PCI controller. There, the ATMU would then translate this to PCI address space - let's say to 0xb000_00FF, and put that transaction out on the PCI bus.

Does that help?

 ... Paul

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Contributor I

Hi,

 

what happens if both PCIe outbound window and prefetch base+limit registers have been configured?

I would like to know about a case if these two are consistent and if they are not.

 

I'm using P2020 processor.

 

Regards,

Pedro

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Contributor I

 

Genuap wrote:
"You can think of LAW's as part of the main system bus. They map addesses on this bus to peripherals. For example, you would have LAW's set up to map:
    Addresses 0 - 0x3FFF_FFFF to DDR
    0x4000_0000-0x4FFF_FFFF to PCI
    0x5000_0000 - 0x5FFF_FFFF to Local Bus
    0x6000_0000 - 0x7000_0000 to RapidIO
This is from the system's point of view (or system bus) so its not an address that the core see's - this is a physical address, past the MMU. Anytime the system bus see's this address it knows where to steer it to."
....
"Outbound ATMU's work similarly. A CPU write to physical address  0x4000_00FF would be steered towards the PCI controller. There, the ATMU  would then translate this to PCI address space - let's say to  0xb000_00FF, and put that transaction out on the PCI bus."

Thanks your post, i understood more, but I have some questions:

 

1. Consider PCI range, are there differences if this CPU is an Agent or a Host?

 

2. When it is a Agent, this PCI range = Outbound Window? And when it is a Host, does it have any relative with PCI's BAR?

 

3. With the LAW'setting above, must I setup the PCI Outbound Window Base Address = Base address of the PCI range in LAW? Need setup size of two windows equal?

 

Zodiac

 

 

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Contributor I

Hello All

 

I am new to Freescale(MPC8641)

 

Could you explain about relocation of CCSR wrt CCSRBAR?

 

All of the memory-mapped configuration, control, and status registers (CCSRs) in this device are

contained within a 1-Mbyte address region. To allow for flexibility, the CCSR block is relocatable in the

local address space. With some exceptions, the CCSRs must be accessed 32-bits at a time. Notable

exceptions are the global timer module, the infrared controller, and the watchdog timer module registers,

and the PCI and PCI Express configuration data ports (CFG_DATA and PEX

support 32-bit, 16-bit, or 8-bit accesses. The DUART and I2C registers must be accessed as single bytes

only.

 

The local address map location of the CCSR block is controlled by the configuration, control, and status

base address register (CCSRBAR);The default value for CCSRBAR is 0x0_FF70_0000 ( 4 Gbytes-9Mbytes).

 

No address translation is performed for CCSR space, so there is no associated translation address

register. The CCSR window is always enabled with a fixed size of 1 Mbyte; no other attributes are

attached, so there is no associated window attribute register.

 

Plese consider code part also:

 

#define CFG_CCSRBAR_DEFAULT    0xff700000   /* CCSRBAR Default */
#define CFG_CCSRBAR      0xf8000000   /* relocated CCSRBAR */

 

Code part:

 

.globl setup_ccsrbar

setup_ccsrbar:

/* Special sequence needed to update CCSRBAR itself */

lis r4, CFG_CCSRBAR_DEFAULT@h

ori r4, r4, CFG_CCSRBAR_DEFAULT@l

lis r5, CFG_CCSRBAR@h

ori r5, r5, CFG_CCSRBAR@l

srwi r6,r5,12

stw r6, 0(r4)

isync

lis r5, 0xffff

ori r5,r5,0xf000

lwz r5, 0(r5)

isync

lis r3, CFG_CCSRBAR@h

lwz r5, CFG_CCSRBAR@l(r3)

isync

blr

 

 

Please send your response.

1.what is local address space? (adress start   &  adress end)

2.how you can relocate & what code is doing.

3.srwi r6,r5,12,what this insruction will do in above code?

 

Thank you very much

Alex

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Contributor I
Paul,
 
 
Thank you for your help.  It was helpful.
 
So, if I were to match up your explanation with the terminology of figure 1-2 of the MPC8641D reference manual ...
 
- when you speak of the 'main system bus' you are refering to the platform bus ?
 
- The ECM is another term for MCM ?
 
- Both the ATMUs and LAWs govern the mapping of addresses on the platform  bus ?
 
- The MMUs are on the other side of the MPX bus, towards the cores ?
 
 
Thank you again.
 
 
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