MPC5668 does not support inter-core exclusive access to shared memory through CAS primitive??

[GangHan]

Recently, I implemented a CAS(compare and swap) based on PowerPC instruction lwarx and stwcx as an inline assembly function.

However, it turns out only the intra-core memory synchronization is supported, while the inter-core one is not. Then, I looked through almost all the related documents to find below information. 

1 In e200z6 PowerPCTM Core Reference Manual pp124

Reservation granularity is implementation dependent. The e200z6 does not define a reservation granule explicitly; it is defined by external logic. When no external logic is provided, the e200z6 does not compare addresses; thus, the effective implementation granularity is null.

2 In PowerPC Microprocessor Family: The Programming Environments Manual for 64-bit Microprocessors pp423
     When the RESERVE bit is set, the processor enables hardware snooping for the block of memory addressed
     by the RESERVE address.
     /******************************************************************/
      If the processor detects that another processor writes to the block of memory it
     has reserved, it clears the RESERVE bit.
     /******************************************************************/

3 However, I found this in MPC5668x Microcontroller Reference Manual pp364

     /******************************************************************/
     Reservation management logic external to the e200z6 is not implemented.
     /******************************************************************/

Who can help me, please?

[TomE · Accepted solution]

> Who can help me, please?

You have already proved the hardware can't do what you want, and written a very good post on that subject with good references.

So what help do you want? I'm assuming you want help on implementing semaphores or mutexes, or a mechanism to support same.

There are lots of books on that subject. Not all CPUs support CAS type instructions, so people have been inventing other ways to do this for a long time. I'd suggest you start here:

http://en.wikipedia.org/wiki/Mutex#Software_solutions

You should be looking for sample code that implements semaphores/locks on existing CPU architectures without reservation. There may be linux ports for various platforms that do all of this already.

Tom

[GangHan]

Actually, I just want to make sure what I stated is right. Because I don't find an explict declaration from freescale that MPC5668G doesn't support inter-core CAS.Maybe I did not express myself clearly.

Thanks!

[TomE]

The MPC5668 is an assymetric part.

The E200Z6 core has FPU, MMU and a cache. The E200Z0 core doesn't have any of these. The second core isdocumented as "Additional e200z0 core to pre-process incoming communication data from high-speed networks".

This can't easily run SMP. The second core is meant as a dedicated IO Processor running its own separate code. You're probably meant to implement memory-based message passing that doesn't require hardware-based semaphores.

Tom