1.
Datasheet Table 3 provides Power Down Current as the current through the PDC pin. PDC uses negative logic and should be grounded if not used (capacitor can be removed). On/Off Voltage levels are provided. VCC1 and VCC2 consumption in the power down mode is low but it is not specified. There is no need for external control of VCC1/VCC2 supplies.
2.
Pins 4 and 5 are not internally connected. They can be left open or grounded.
3.
These leads are connected by wire bonds to the common pad on the die. So, they are electrically tied together. However, each wire bond introduces some inductance. On the evaluation board, one pin is used for DC bias to separate RF path from DC bias. Doing that may increase VBW of the circuit. It is not mandatory to separate connections. Though, i suggest to follow reference design.