R1 and R2 define reference currents for current-mirror bias circuit.
The bias circuit is similar to one from the Figure 5 of the application note AN3100:
https://www.nxp.com/docs/en/application-note/AN3100.pdf
MMZ09332BT1 provides separate bias circuits for two stages.
The Stage 1 operates in class A amplifier mode. Indeed, the small signal gain of HBT CE amplifier depends on the quiescent current. So, R1 can be used to control the gain of the Stage 1. But have in mind that NXP reference designs have been optimized at certain quiescent currents and you will need to tune impedance matching circuits for different current setting.
Stage 2 works in class AB amplifier mode. It is a high power non-linear mode. Average collector current can be much more than the quiescent current. So, the gain would depend on the signal level. In this mode, the quiescent current can be used to optimize Gain-vs-Pout linearity of the amplifier. Optimal quiescent current will provide near flat Gain-vs-Pout slope similar to Figure 10 of the datasheet. Too small ICC2 current will cause rising gain slope.
Quiescent currents values in NXP reference designs are selected to provide specified power and gain performance. Decreasing these currents will case lower gain and max power.
Have a great day,
Pavel
NXP TIC
