MC56F84786 SPI CS Pin Timing Configuration

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MC56F84786 SPI CS Pin Timing Configuration

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20Sidar04
Contributor III

Dear Mr. and Mrs.,

I couldnt find any configuration for timing CS pin like configuration of SPC series PowerPC controller on CodeWarrior. I need this because When I set CS pin end of sending dummy data, Pin is getting high during data send. Due to this reason, I faced with problem which getting data from SPI line. Should I solve this problem by setting CS pin after getting data. Is there any register for timing of CS pin. Thanks in advance for precious supports.

Regards.

Sidar.

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

when you configure the SPI in master mode, the /CS signal can be driven automatically or drive as a Gpio pin.

If you want to drive /CS automatically when the SPI transfer data, pls configure the register.

xiangjun_rong_0-1699413145600.png

 

You should configure SSB_DDR=1, SSB_AUTO=1, SSB_ODM=0, SSB_STRB=1 if you want the SPI master to drive the SS automatically.

Pls have a try

BR

XiangJun Rong

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

when you configure the SPI in master mode, the /CS signal can be driven automatically or drive as a Gpio pin.

If you want to drive /CS automatically when the SPI transfer data, pls configure the register.

xiangjun_rong_0-1699413145600.png

 

You should configure SSB_DDR=1, SSB_AUTO=1, SSB_ODM=0, SSB_STRB=1 if you want the SPI master to drive the SS automatically.

Pls have a try

BR

XiangJun Rong

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20Sidar04
Contributor III

Dear @xiangjun_rong 

After configuring Microcontroller as following your decription, The CS pin is pulled high after each byte. But I want the CS pin keep low until the last byte transfer is completed. How can i solve this problem?

Regards.

Sidar

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20Sidar04
Contributor III

Following picture is describe my problem. Other microcontroller IDE has configuration to keep cs low pin until last data byte transfer. Such as S32  PCS continuous checkbox.

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

I have checked the spi timing in the attached picture, obviously, the waveform is correct, the /CS low interval covers the data transfer.

If you do want to clear the /CS until all data are transferred, you can use any GPIO pin or just configure the /CS pin of master spi as GPIO output mode, not all the peripherals pins are multiplexed with GPIO. First of all, just configure the /CS pin as GPIO output mode, before you transfer any data, clear the GPIO, after the transfer is over, set the GPIO pin.

Hope it can help you

BR

XiangJun Rong

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