MC17XSG/MC32XG problem with connecting to device

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MC17XSG/MC32XG problem with connecting to device

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mehrdad_ostovar
Contributor I

Hi,

I have to implemet the MC17XSG on K10 CPU with SPI and have big problems.

When I Set the IN1-4 then the output 1-4 goes high. This means that the device is in some kind of fail mode.

Then I try to read the register which reflects at least the IN1-4 and OUT1-5.

I send the message 0x0408 and read no answer (all bits are 0) then I send again 0x0408 and receive again nothing.

Then I tried to send following commands:

 dspi_Write( tpHSData, 0, 0x401, &iDataReceived);      //Write to register 0 the value 0x401
dspi_Write( tpHSData, 0, 0x402, &iDataReceived);
dspi_Write( tpHSData, 0, 0x403, &iDataReceived);
dspi_Write( tpHSData, 0, 0x404, &iDataReceived);
dspi_Write( tpHSData, 0, 0x405, &iDataReceived);
dspi_Write( tpHSData, 0, 0x406, &iDataReceived);
dspi_Write( tpHSData, 0, 0x407, &iDataReceived);
dspi_Write( tpHSData, 0, 0x408, &iDataReceived);
dspi_Write( tpHSData, 0, 0x401, &iDataReceived);
dspi_Write( tpHSData, 8, 0x1F, &iDataReceived); //Turn on all outputs (write to register 8 , 0x1F, ON1-5)

These sequence will be sent every 20ms and watchdog bit is changing at every sequence. The device was running with 2MHz clock but I reduced it to 700KHz but no change.

Whe Chipselect goes down (active) then I see on Osciloscope that there is change in level of few mV and when CS goes high the same in other direction.

I have absolutley no idea why and the data ´sheet is no help at all.

To NXP Stuff: the datasheet of this device is the worst datasheet I ever saw in my life. It is wrong, written in a way that you can understand it wrong and the key sections are moved all around the sheet and not in one place. I never had so much problems to understand a device. You should delete this datat sheet and write it new. There are also wrong information in it. Once: the SI data will be latched at rising edge, in diagram it latched in falling edge. MAKE YOUR JOB AND WRITE A READABLE AND CORRECT DATASHEET!!!

I would be happy if somebody can help me.

Thanks in advance

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6 Replies

216 Views
mehrdad_ostovar
Contributor I

Please see also the below picture from Oscilloscope. Chanel 1 (bottom) is CS, Channel 2 is SPI-SCK, Channel 3 is MOSI (SI) and channel 4(top) is MISO (SO).

You see the very interesting change in the level!!! Device is powered by 5V. When the device output its SO, its at level of ~3V and when the SI drops to 0V then the SO rises to 5V and back again to 3V at next clock!!!??? Whats that?

pastedImage_1.png

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216 Views
TomasVaverka
NXP TechSupport
NXP TechSupport

Hi Mehrdad,

Please accept our apologies for the delay in answering your question, but our application engineer who is in charge of this device has been busy this week and could not look deeply into this issue.

 

Here is an initial feedback including few questions.

 

What is the Vdd value?

What is the VBAT value?

Is the Limp pin at 1? Recommendation: keep the Limp limp pin at 0.

If you can control with direct input while the Limp pin=0, then it should a SPI failure has been detected, the device is in Fail mode.

Looks to be SPI timing related. Did you already run this device with SPI in the past?

 

Thank you for your honest feedback on the data sheet. This is what we need to hear in order to improve it!

Best regards,

Tomas

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216 Views
mehrdad_ostovar
Contributor I

Hi,

I solved this problem but I have now a bigger problem.

I get no correct answer from device. It seems the communication is wrong. First of all, There is no correct information about SPI communication and the datasheet is very uncomplete. It seems like a early beta version.

1.) In page 15 it says that the SI is latched on the rising edge of clock and in page 20 in diagram its the falling edge.

2.) The SO diagram contains no information at all.

3.) the kind of showing information is wrong. 

pastedImage_1.png

You display both valid and dont care in the same way but it have to be different like this:

pastedImage_2.png

in this picture there is no need to explain if data is valid or not.

4.) There is the time t(WRST) which is the time from reset release to CSB low but there is nowhere the deffinition of this time.

5.) In the description of SO on page 6 you describe that the signal can be used for daisy chain but there is no explanation how to do that.

6.) The explaination of CLK is very bad and let a lot of room for misunderstanding.

but now to my main problem:

I'm using K10DN CPU. We dont use PWM-Mode, so the clock is static.

I tried all SPI Parameter: kDspiMsbFirst, kDspiLsbFirst, kDspiClockPolarity_ActiveLow, kDspiClockPolarity_ActiveHigh, kDspiClockPhase_FirstEdge, kDspiClockPhase_SecondEdge in a lot of combinations but there is no correct answer. I see on the signal that the device is sending something but not the requested information. It seems also that the device dont receive the correct values because I'm not able to switch the output.

when I send the messages 0x0005 then I should receive in the next message something like 0x5xxx. but I get always 0x0xxx. with some SPI configuration I get like 0x0xxy where y is the register number of the last request.

I also dont know exactly how to turn on/off outputs when I dont use IN1-4. When I switch IN1-4 then the output will follow the signal.

Please let me know which SPI configuration have to be used and which values schould I send to device and what should come back.

Please let me also know how to turn on/off the outputs when I dont use IN1-4.

Right now, I stopped programming this device and I need very urgently a solution.

Thanks for your help.

Best regards,

M. Ostovary

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216 Views
TomasVaverka
NXP TechSupport
NXP TechSupport

Hi Mehrdad,

This is just to inform you that I should have answers to your questions on Thursday, May 2nd.

Thank you for your patience.

Best regards,

Tomas

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216 Views
TomasVaverka
NXP TechSupport
NXP TechSupport

Hi Mehrdad,

Here are the answers to your questions:

1. Sorry if unclear, it is necessary to understand that SI is subject to change its state at rising edge of clock and is acknowledge at falling edge.

2. Figure 12 on page 21 is showing the relevant timing information for SO.

3. Both diagrams are not showing the same understanding. The one from spec above is showing in 2 periods of clock that data from SI that is acknowledged at falling edge and we “don’t care” the SI state during the SCLK rising edge. The one below is showing in addition with timings that on a full SPI frame (whatever 8, 16 or more modulo 8 bits) SPI frame is MSB first.

Actually the “don’t care” area is shown in this picture with that symbol: pastedImage_7.png

4. This is indeed an omission on that specification. This required low state of RST/ is 1us. I’ll add it in a potential next spec update.

5. There are plenty of application notes on the web regarding SPI daisychain like this one.

6. SPI Clock pin or input clock for PWM? Could you be more specific?

I'm using K10DN CPU. We don’t use PWM-Mode, so the clock is static.

I tried all SPI Parameter: kDspiMsbFirst, kDspiLsbFirst, kDspiClockPolarity_ActiveLow, kDspiClockPolarity_ActiveHigh, kDspiClockPhase_FirstEdge, kDspiClockPhase_SecondEdge in a lot of combinations but there is no correct answer. I see on the signal that the device is sending something but not the requested information. It seems also that the device doesn’t receive the correct values because I'm not able to switch the output.

>> To get the device answer with at least DSF bit (D10=1) you should get the following condition: RSTB=VDD=5V / no clock / and valid SPI communication < 4MHz with MSB first, CSB asserted low, SCLK low before/after transfer, SI/SO toggled at rising edge but valid and acknowledged at falling edge. You then need 2 successive commands with WD bit toggled (MOSI bit D11 changing 0 to 1 at each SPI access) to get the device in normal mode.

When I send the messages 0x0005 then I should receive in the next message something like 0x5xxx. But I get always 0x0xxx. With some SPI configuration I get like 0x0xxy where y is the register number of the last request.

I also don’t know exactly how to turn on/off outputs when I don’t use IN1-4. When I switch IN1-4 then the output will follow the signal.

Please let me know which SPI configuration have to be used and which values should I send to device and what should come back.

>> In the configuration depicted above, if you send twice 0x0001 to SI, you should get back 1Cxx (where xx depends if output loaded or not). If you do the same but toggling watchdog (0x0001 then 0x0801) you should get 0x14xx.

Please let me also know how to turn on/off the outputs when I don’t use IN1-4.

>> You need to 1st fix SPI communication problem then turn ON can be accomplished with CHx control with bit D8=1 (keeping the WD toggle alive within its timeout period).

Please let us know if there are any other questions.

Best regards,

Tomas

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216 Views
mehrdad_ostovar
Contributor I

Hi,

I cheked that and change my configuration and this the results of my programm output:

Read all regs
HS-SPI TX: 0x0401, Rx: 0x1DE9
HS-SPI TX: 0x0C02, Rx: 0x1D09
HS-SPI TX: 0x0403, Rx: 0x1D4B
HS-SPI TX: 0x0C04, Rx: 0x3503
HS-SPI TX: 0x0405, Rx: 0x4D04
HS-SPI TX: 0x0C06, Rx: 0x5507
HS-SPI TX: 0x0407, Rx: 0x6D06
HS-SPI TX: 0x0C08, Rx: 0x7507
HS-SPI TX: 0x0401, Rx: 0x8F38

Write all regs
HS-SPI TX: 0x0C00, Rx: 0x1501
HS-SPI TX: 0x1000, Rx: 0x1D01
HS-SPI TX: 0x2800, Rx: 0x1101
HS-SPI TX: 0x3000, Rx: 0x3901
HS-SPI TX: 0x4800, Rx: 0x3101
HS-SPI TX: 0x5000, Rx: 0x5901
HS-SPI TX: 0x6800, Rx: 0x5101
HS-SPI TX: 0x7000, Rx: 0x7901
HS-SPI TX: 0x881F, Rx: 0x7101
HS-SPI TX: 0x9000, Rx: 0x991F
HS-SPI TX: 0x9C00, Rx: 0x9101
HS-SPI TX: 0xA000, Rx: 0x9D01
HS-SPI TX: 0xAC00, Rx: 0xB101
HS-SPI TX: 0xB000, Rx: 0xBD07
HS-SPI TX: 0xC800, Rx: 0xB107
HS-SPI TX: 0xC400, Rx: 0xD907
HS-SPI TX: 0xD800, Rx: 0xD507
HS-SPI TX: 0xD400, Rx: 0xD907
HS-SPI TX: 0xE800, Rx: 0xD507

The read registers seems to be OK but its not OK because on the second line I request the Register 2 but I get register 1 as answer with totally diferent content. I receive as answer to read register 8, 0x8F38 back. This is correct because I turned on IN1 and IN4 and the OUT5 is pushed to high by a short to +12V and as you see. the fail mode toggels as the WD bit is toggeled!!!???? As you see in the register readings the Bit 11 reflects the WD state and not the FM flag!!!??? And in register writing only odd registers are returned. When WD bit is high, the returned address is not correct and content seems also to be wrong. I cant proove that.

I also changed to toggle WD bit only when reading status but the result is nearly the same. see below:

pastedImage_1.png

As you see, the requests and the answers are partly total different.

Hier you see the decoded values from logic analyzer in text:

Time [s],Packet ID,MOSI,MISO
1= 6.939786600,0,0x0401,0x1DE9
2 = 6.944713720,1,0x0C02,0x1D09
3 = 6.949718980,2,0x0403,0x1D4B
4 = 6.954720680,3,0x0C04,0x3503
5 = 6.959722120,4,0x0405,0x4D04
6 = 6.964718780,5,0x0C06,0x5507
7 = 6.969718140,6,0x0407,0x6D06
8 = 6.974725880,7,0x0C08,0x7507
9 = 6.979727940,8,0x0401,0x8F38
10=6.986123060,9,0x0400,0x1501
11=6.991730680,10,0x1000,0x1D09
12=6.996757300,11,0x2000,0x1909
13=7.001739440,12,0x3000,0x3909
14=7.006729980,13,0x4000,0x3909
15=7.011729800,14,0x5000,0x5909
16=7.016737700,15,0x6000,0x5909
17=7.021775560,16,0x7000,0x7909
18=7.026825580,17,0x801F,0x7909
19=7.031735660,18,0x9000,0x991F
20=7.036743600,19,0x9400,0x9909
21=7.041745360,20,0xA000,0x9D09
22=7.046746020,21,0xA400,0xB909
23=7.051741420,22,0xB000,0xBD09
24=7.056749720,23,0xC000,0xB909
25=7.061751180,24,0xC400,0xD909
26=7.066773100,25,0xD000,0xDD09
27=7.071759640,26,0xD400,0xD909
28=7.076755700,27,0xE000,0xDD09

In line 1 I ask for Register 1 and get back register 1 (0x1DE9, this is from previous request).

In line 2 I ask for Register 2 and get back Register 1 (0x1D09).

In line 3 I ask for Register 3 and get back Register 1 (0x1D4B). Why register 1? I asked for register 2.

The next question is why I get for the same register totally different values. This register cant change so much within ~5ms. Why is the FM always active? The WD bit is altering.

Allways when I ask for something witth WD bit set, I get back with D11 set and not the correct value.

The device seems to have total different behavior than written in datasheet.

The Main problem is that the device is not doing as written in data sheet and during my test ALWAYS in fail mode because the outputs are all set to 1 but only around every second the device turn on the ouputs for ~250ms and then turn it off again. I also cant debug the device because of the fucking WD. I dont understand how  manufacturer can product a device which cannot disable the watchdog specially after power on.

I still cant work with the device.

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