Hello,
each interrupt ID corresponds to a cluster,
the LX2160A has a Sixteen 32-bit/64-bit Arm v8 A72 CPUs arranged as clusters of two cores sharing a 1 MB L2 cache, it means if there is any error on one core the assigned cluster will trigger the corresponding interrupt, those interrupts are ORed and connected to GIC at the mentioned ID slots, for more information about the interrupts you can refer to the ARM GIC manual.
