Hi @jamesbone, @sureshrao, @dbaluta ,@serguei,@Tomas
Hi I m using LS1028A Processor for my project. I want more clarifications on JTAG Interface for LS1028A. I was referring to the document named "QorIQ LS1028A Design Checklist" to know about Jtag Interface requirement. In pg-54 of the document, they have shown a logic gate circuit for "TRST_B". Can u please elaborate the circuit in terms of the dependent variables for the jtag access and in terms of timing requirement?
I have few doubts related to that-
1) TRST_B signal has a timing requirement as stated by Processor's datasheet as shown below. Who shall provide TRST_B with the given timing?
2) Is there any timing relation between PORESET_B and TRST_B ?
3) If we have an option to dismiss the usage of the logical gate, where shall the nRESET from Codewarrior to be connected ?
