LS1028A JTAG Interface

[Rashmita]

Hi I m using LS1028A Processor for my project. I want more clarifications on JTAG Interface for LS1028A. I was referring to the document named "QorIQ LS1028A Design Checklist" to know about Jtag Interface requirement. In pg-54 of the document, they have shown a logic gate circuit for "TRST_B". Can u please elaborate the circuit in terms of the dependent variables for the jtag access and in terms of timing requirement?

[jamesbone]

The logic gate, it is to avoid when you are performing a POR reset,  that the device get the TRST signal of the JTAG.   If you are not planning to use the POR_B signal you can dismiss the usage of the logical gate.

[Rashmita]

Hi @jamesbone 

I have few queries regarding same topic -: 

1) TRST_B signal has a timing requirement as stated by Processor's datasheet as shown below. Who shall provide TRST_B with the given timing?

2) Is there any timing relation between PORESET_B and TRST_B ?

3) If we have an option to dismiss the usage of the logical gate, where shall the nRESET from Codewarrior to be connected ?

[Rashmita]

Please LS1028A Design Checklist (AN12028)  figure 36