LDMOS Vgs protection

[jplathuile]

Hi,

I intend to make an HF amplifier that uses LDMOS (MRF101).
As the band will be wide the driver have not a flat response.
Vgs max is quite tight, I can read on that forum that it is a cause of problem.
The device is said to be "esd enhanced" which seem to mean that it can accept VGS negative. But not much is said about esd sensitivity.
So I intend to protect the gate with a tvs diode, what is your opinion about, or what protection will you suggest.

Regards,

JP Lathuile

[jplathuile]

Ok, I was meaning for different transistor

AFT05MS004NT1 Zin=5.06 + j12.97 at 175MHz gain 17db
MRF101 Zin= 3.9 + j13.4 at 175 gain 21db
MRF 300 1.77 + j1.90 at 230

All have a -6V < Vgs max< 10V but as Zin is lower Vin is not increasing in proportion. And we stay far from Vgsmax.

JP

[LPP]

That's right. In RF power transistor many fingers are placed in parallel to form a power die. More powerful transistor have more LDMOS fingers in parallel. That's why it's impedance gets smaller.

The threshold voltage is an independent parameter that is specific for each transistor. The boron p-type  diffusion establishes the threshold voltage and turn-on characteristics of the device. There is no relation of this parameter to the power rating of the transistor.
https://www.nxp.com/docs/en/white-paper/50VRFLDMOSWP.pdf

Pavel

NXP CAS

[LPP · Accepted solution]

MRF101AN LDMOS transistor implements enhanced ESD protection of the gate.
https://www.nxp.com/docs/en/white-paper/50VRFLDMOSWP.pdf

The ESD protection circuit is similar to that described in this Ampleon document (spun off from the NXP Semiconductors in 2015):
https://www.ampleon.com/documents/white-paper/AMP-WP-2017-0329.pdf.pdf

This protection circuit does not rectificate input signal, and the bias voltage does not shift under the most severe conditions. The presence of internal protection makes the use of external TVS protection of MRF101AN gate unnecessary.

[jplathuile]

Hi,

I already have seen the first text, but the second (from ampleon) is very interesting.
So there no need for esd diode, my first evaluation was with Zin (gate impedance) near 50 ohms, but as these transistors gets more powerfuls, Zin goes lower. And input tension stays low.

JP

[LPP]

It is a very common case. LDMOS transistor is a non-linear device. It's optimum input and output impedances depend on available input power. On the other hand, the matching networks are almost linear circuits. So, it is not possible to match transistor impedances over wide power range.

Most cases, the matching networks are optimized to achieve maximum performance (power, gain or PAE) at maximum power (P1dB or sometimes at P3dB gain compression level). Such circuits will be matched at the target power and mismatched at low power.

For classAB mode amplifier, the gain vs power curve slope depends on the quiescent current. This current can be optimized to achieve maximum flat gain curve. For example, see MRF101AN datasheet Figure 49.

Pavel

NXP CAS

[jplathuile]

Ok

JP