Initialization of RTC PCA21125

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Initialization of RTC PCA21125

Contributor IV


I am trying to interface the PCA21125 RTC with the MPC5745R, through SPI. I find it difficult to comprehend the initialization part of the documentation for the RTC. 

Could you please clarify if my understanding is correct? Steps for initialising the RTC.

1. Initialize the SPI as MASter

2. (Not sure part) Set the POR_OVRD bit. I would assume that the POR_OVRD bit would be set if a reset had occured already. I don't completely understand the connection between the POR_OVRD bit and the RF bit (in the seconds reigster). 

3. If the POR_OVRD bit is set, this means the RTC is available for configuration. So then write the desired time registers. Then clear the POR_OVRD bit. 

Is this workflow correct? Also I would like to understand if the EXT_TEST bit should be set for configuration? I understand/think that it is possible to re-configure/initialize when the RTC is running in normal mode itself. but just clarifying. 

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NXP TechSupport
NXP TechSupport


There is no need to have the POR_OVRD bit  set to initialize or configure the RTC, this bit is used to immediately released the device from the reset state and the set-up operation can commence for cases where you require to start really quickly with the configuration.

Due to the long start-up times experienced by these types of circuits caused by the start-up of the crystal oscillator, a mechanism has been built in to disable the POR and hence speed up the on-board test of the device. This mechanism is the POR_OVRD bit.


By default on the PCA21125, the POR_OVRD bit is set (‘1’), so, Power-On Reset Override sequence reception is enabled by default. The override mode can be cleared by writing logic 0 to bit POR_OVRD. Setting bit POR_OVRD logic 0 during normal operation is the recommended setting.


To configure the time (write to time registers), the SPI-bus needs to be initialized by an active HIGH chip enable signal CE and terminated by an inactive LOW signal.

The first byte transmitted is the command byte (see Table 40 and Figure 20).

Subsequent bytes are either data to be written or data to be read. Data is captured on the rising edge of the clock and transferred internally on the falling edge.


The command byte defines the address of the first register to be accessed and the read/write mode. The address counter will auto increment after every access and will reset to zero after the last valid register is accessed.



About EXT_TEST bit, this bit should not be set for configuration, for normal operation, EXT_TEST bit should be ‘0’.

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