I'm now starting with the MPC5643L Reference Manual, and looking to see how someone new to this family of CPUs could find out about the bit ordering convention.
Starting with the Reference manual, the CPU chapter (Chapter 17, e200z4d Core Complex Overview) lists a few registers numbered in IBM order, and at the end refers to:
17.5 Availability of detailed documentationDetailed documentation of the e200z4d core is provided in a separate core reference manual (CRM). ThisCRM is available online at http://www.freescale.com.
I'm looking at that document, and it assumes you already know everything about the architecture as well.
There's nothing obviously useful linked from the MPC5643L's web page either.
But I happen to know (from when the product mix was simpler) that what we're looking for is called the "PEM", so if you search for that you'll find references to "MPCFPE32B.pdf", which is the "Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3".
In the "Overview" section of that document it states:
Programming model—The programming model defines the register set and the memoryconventions, including details regarding the bit and byte ordering, and the conventions for howdata (such as integer and floating-point values) are stored.
"bit and byte ordering", so we're getting closer... After all, this is the "PROGRAMMING Environments Manual".
Then I find "Figure 1-2. Big-Endian Byte and Bit Ordering" in a section which details all the BYTE order options, but doesn't mention anything about the BIT order at all.
Surely the Register Set section will detail this? Nope.
So it must be detailed somewhere else. Maybe from here:
Related DocumentationFreescale documentation is available from the sources listed on the back cover of this manual; thedocument order numbers are included in parentheses for ease in ordering:• EREF: A Programmer’s Reference Manual for Freescale Book E Processors—This book providesa higher-level view of the programming model as it is defined by Book E and the Freescale BookE implementation standards.
So it must be in the EREF? There's pretty much a whole chapter in the EREF detailing all the books, what they were called, what they are called and how they're related to other books - here's a SMALL sample of how it goes on:
About This BookThe primary objective of this reference is to provide software and hardware designers with the ability todesign and program to the instruction set architecture (ISA) defined for embedded environment processorsby the Power ISA™ and by Freescale’s implementation standards (EIS).The Power ISA Architecture Specification and the Freescale EISBook I and Book II have been reorganized and amended, with features essentially unchanged fromBook E, the EIS, and IBM’s PowerPC 2.02 specification for server processors. Although Book III-E andBook III-S still bear a family resemblance to the original PowerPC Book III definition, they differ in verysignificant ways both from one another and from the PowerPC 1.10 specification.
...
General Information
The following documentation provides useful information about Power Architecture technology and
computer architecture in general:
• Power ISA™ Version 2.05, by Power.org™, 2007, available at the Power.org website.
• PowerPC Architecture Book, by Brad Frey, IBM, 2005, available at the IBM website.
• Computer Architecture: A Quantitative Approach, Fourth Edition, by John L. Hennessy and David
A. Patterson, Morgan Kaufmann Publishers, 2006.
• Computer Organization and Design: The Hardware/Software Interface, Third Edition, by David
A. Patterson and John L. Hennessy, Morgan Kaufmann Publishers, 2007.
But there's nothing on the BIT order that I can find. I can only guess that it perhaps might be in one of the first two books listed above, the "Power ISA..." or "PowerPC Architecture...".
I'm giving up this chase here.
Otherwise this is It looks like this is "just something you have to know" or something you're meant to "pick up by osmosis or revelation", or by looking at the 1950's IBM computer control panel I linked to in my previous email.
And of course to access bit "n" in the Power chips as numbered in all of the manuals, instead of using "1<<n" you can use "0x80>>n" or "0x8000>n" or "0x80000000>>n" depending on access size. But if you do that, then some of your code will be using one convention and the rest will be using "2^^n" and you'll find yourself in all sorts of trouble. Been there, done that.
Tom
