Inconsistent bit numbering? (MPC5643L)

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Inconsistent bit numbering? (MPC5643L)

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bjn
Contributor I

Take a look at this short code and tell me what you think.

 

int main(void)
{
  volatile unsigned int i = 0;
 
  DisableSoftwareWatchdog();
  InitializeModesAndClock();
 
  init_IO();

  /* Loop forever */
  for (;;) 
  {
    /* Toggle LED @ PD4, through GPDO */
   
    SIUL.GPDO52.R ^= 1<<7;   /* Doesn't work. According to datasheet
                                bit 7 in GPDO52 handles this IO, but
                                nothing happens when this code is
                                executed */
    asm(nop);
   
    SIUL.GPDO52.R ^= 1<<0;   /* This works. It seems the bit numbers are
                                written backwards in datasheet (they are
                                numbered from left to right in datasheet
                                but probably supposed to be numbered
                                from right to left(?)) */
    asm(nop);


    /* Toggle LEDs @ PD5-6, through PGPDO */
   
    SIUL.PGPDO3.R ^= 0x0060; /* This should toggle bits 5-6, right?
                                but this line does nothing to PD5-6. */
    asm(nop);
   
    SIUL.PGPDO3.R ^= 0x0600; /* Lets try this. Now PD5-6 are toggled.
                                it seems that this time the bits in
                                the chip is numbered from left to right,
                                just like in the datasheet. But this is
                                backwards from every digital logic
                                convention, right? */
    asm(nop);
   
 
    /* Delay */
    i = 0x00020000;
    while(--i)
    {
      ;
    }
  }
}

 

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TomE
Specialist I

What do I think? I think you don't know what you're doing. You did ask... Smiley Happy

 

From the Reference manual:

 

47.5.2.10 GPIO Pad Data Output Registers (GPDO)

 

The GPDO registers are 32 bits wide, but are designed so you can access this as any one of four bytes. One byte access can set or clear a single pad without interfering with any other ones. The bit in that byte is bit "7" which is the least significant bit.

 

(they are numbered from left to right in datasheetbut probably supposed to be numberedfrom right to left(?)) */

Every bit in every register on all 1394 pages of the manual are numbered that way, so you can be sure they really mean it.

 

The bits are numbered "from the left" which is also the MSB with the LSB being bit 7, 15 or 31 depending on the access because back in the 1950's someone at IBM numbered their computer's bits that way. Click on the following to see an example:

 

http://upload.wikimedia.org/wikipedia/commons/6/6a/IBM360-65-1.corestore.jpg

 

The MPC parts have a "Power" core, meaning IBM, meaning the bits are that way.

 

But this is backwards from every digital logicconvention, right? */

Nope. They're numbered according to IBM's convention. You've heard of Big and Little Endian Byte Order? That's IBM/Motorola vs Intel (mainly). Well there's also bit-order conventions too.

 

Refer here for more info from when I was in a better mood with a less arrogant poster Smiley Happy

 

https://community.freescale.com/message/84050#84050

 

Tom

 

 

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bjn
Contributor I

Hi Tom, thanks for your replies. MPCFPE32B.pdf seems like a good read.

 

Oh man... I wrote this long reply with references to your posts, and where I was describing my background and how all my colleagues agreed with me on how backwards this is bit numbering system is. But he post got **bleep**ing lost when I tried to post it. Oh well, it was probably not of much interest anyway.

 

I'll just have to accept it, and hope I'll wake up in the middle of the night with bits circulation in front of my eyes every time i need to realise which bugs needs to be fixed the next day.

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bbx
Contributor I

I'm glad I found this thread - I'd just spent half a day thinking I'd lost the plot. 

 

 If I have ever encountered this madness before my brain must have erased all memories.

 

 

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TomE
Specialist I

I'm now starting with the MPC5643L Reference Manual, and looking to see how someone new to this family of CPUs could find out about the bit ordering convention.

 

Starting with the Reference manual, the CPU chapter (Chapter 17, e200z4d Core Complex Overview) lists a few registers numbered in IBM order, and at the end refers to:

 

17.5 Availability of detailed documentationDetailed documentation of the e200z4d core is provided in a separate core reference manual (CRM). ThisCRM is available online at http://www.freescale.com.

I'm looking at that document, and it assumes you already know everything about the architecture as well.

 

There's nothing obviously useful  linked from the MPC5643L's web page either.

 

But I happen to know (from when the product mix was simpler) that what we're looking for is called the "PEM", so if you search for that you'll find references to "MPCFPE32B.pdf", which is the "Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3".

 

In the "Overview" section of that document it states:

 

Programming model—The programming model defines the register set and the memoryconventions, including details regarding the bit and byte ordering, and the conventions for howdata (such as integer and floating-point values) are stored.

"bit and byte ordering", so we're getting closer... After all, this is the "PROGRAMMING Environments Manual".

 

Then I find "Figure 1-2. Big-Endian Byte and Bit Ordering" in a section which details all the BYTE order options, but doesn't mention anything about  the BIT order at all.

 

Surely the Register Set section will detail this? Nope.

 

So it must be detailed somewhere else. Maybe from here:

 

Related DocumentationFreescale documentation is available from the sources listed on the back cover of this manual; thedocument order numbers are included in parentheses for ease in ordering:• EREF: A Programmer’s Reference Manual for Freescale Book E Processors—This book providesa higher-level view of the programming model as it is defined by Book E and the Freescale BookE implementation standards.

So it must be in the EREF? There's pretty much a whole chapter in the EREF detailing all the books, what they were called, what they are called and how they're related to other books - here's a SMALL sample of how it goes on:

 

About This BookThe primary objective of this reference is to provide software and hardware designers with the ability todesign and program to the instruction set architecture (ISA) defined for embedded environment processorsby the Power ISA™ and by Freescale’s implementation standards (EIS).The Power ISA Architecture Specification and the Freescale EISBook I and Book II have been reorganized and amended, with features essentially unchanged fromBook E, the EIS, and IBM’s PowerPC 2.02 specification for server processors. Although Book III-E andBook III-S still bear a family resemblance to the original PowerPC Book III definition, they differ in verysignificant ways both from one another and from the PowerPC 1.10 specification.
...
General Information
The following documentation provides useful information about Power Architecture technology and
computer architecture in general:
• Power ISA™ Version 2.05, by Power.org™, 2007, available at the Power.org website.
• PowerPC Architecture Book, by Brad Frey, IBM, 2005, available at the IBM website.
• Computer Architecture: A Quantitative Approach, Fourth Edition, by John L. Hennessy and David
A. Patterson, Morgan Kaufmann Publishers, 2006.
• Computer Organization and Design: The Hardware/Software Interface, Third Edition, by David
A. Patterson and John L. Hennessy, Morgan Kaufmann Publishers, 2007.

 But there's nothing on the BIT order that I can find. I can only guess that it perhaps might be in one of the first two books listed above, the "Power ISA..." or "PowerPC Architecture...".

 

I'm giving up this chase here.

 

Otherwise this is It looks like this is "just something you have to know" or something you're meant to "pick up by osmosis or revelation", or by looking at the 1950's IBM computer control panel I linked to in my previous email.

 

And of course to access bit "n" in the Power chips as numbered in all of the manuals, instead of using "1<<n" you can use "0x80>>n" or "0x8000>n" or "0x80000000>>n" depending on access size. But if you do that, then some of your code will be using one convention and the rest will be using "2^^n" and you'll find yourself in all sorts of trouble. Been there, done that.

 

Tom

 

 

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TomE
Specialist I

If you can't find it at Freescale you can usually find it on Wikipedia:

 

http://en.wikipedia.org/wiki/Bit_numbering

 

Tom

 

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