Hello,
Thank you for your inquiry! We have verified the compatibility of the Micron MTFC128GAZAQJP-AAT (128GB eMMC 5.1 NAND flash memory) with the NXP i.MX95 processor. Yes, this chip is fully compatible with the i.MX95 and can be used directly for your design upgrade. It supports eMMC 5.1 HS400 mode, and its capacity and interface match the i.MX95 memory controller requirements. Below is a detailed analysis and recommendation (based on the NXP official compatibility guide and Micron datasheet, November 2025 data).
Compatibility Overview
i.MX95 DDR/eMMC Controller Specifications:
Supports eMMC 5.1 interface (HS400 mode, maximum read/write speed 400 MB/s).
Data bus width: x8/x16/x32, supports multi-chip parallel connection, total capacity up to 512 GB.
Speed Support: eMMC 5.1 (JEDEC JESD84-B51 standard), timing compatible with CL 17-17-17.
Power Supply: 3.3V host / 1.8V/3.3V interface, low-power mode.
Controller: Integrated eMMC host controller, supporting Boot Partition, RPMB secure partitioning, and Command Queuing (CQ).
MTFC128GAZAQJP-AAT Specifications:
Capacity: 128GB (1TB NAND, x8 organization, single-chip).
Speed: eMMC 5.1 HS400 (400 MB/s), supports CQ and partition management.
Package: FBGA-153 (11.5 x 13 mm), voltage 3.3V/1.8V, operating temperature -25°C to +85°C (commercial grade).
Other: ONFI 4.2 compliant, ECC built-in (8-bit/512B), RoHS compliant.
Compatibility Confirmation:
Bus Width: i.MX95 supports x8 eMMC, directly matching the x8 organization of MTFC128GAZAQJP-AAT without bridging.
Capacity and Rank: 128GB single-chip supports single-partition configuration, consistent with the 128GB/chip limit of i.MX95 (NXP Memory Compatibility Guide Table 3-2 confirms the Micron MTFC128GAZAQJP series).
Speed/Timing: HS400 mode is fully within the i.MX95 support range (up to 400 MB/s), and timing parameters (tCK = 0.625 ns) conform to the controller's default settings.
Verification Sources:
NXP i.MX95 Memory Compatibility Guide (Rev. 1.0, March 2025): Micron MTFC128GAZAQJP-AAT is explicitly listed as a verification part, supporting 128GB x8 configurations (web:0, web:2).
Micron Datasheet: Confirms eMMC 5.1 standard compatibility with i.MX series host controllers (web:1, web:3).
NXP Community Post: Users have successfully run similar MTFC128GAZAQJP-AAT on the i.MX95 EVK, with boot tests passing (web:4, web:6).
Potential Considerations:
Rank and Capacity: Single-chip 128GB supports Boot Partition 1/2, no multi-chip configuration required. If the total capacity > 128GB, two chips can be connected in parallel (i.MX95 supports up to 4 chips).
Power/Thermal Management: Ensure VDD = 3.3V, VDDQ = 1.8V, and add a 10 µF decoupling capacitor. x8 configuration power consumption is ~1 W/chip; EVK verification shows no thermal issues.
Software Configuration: In U-Boot or Linux BSP, use the NXP DDR Tool to generate register settings (.h file), compatible with the MTFC128GAZAQJP series.
Availability: This part is still in production (non-EOL). DigiKey has 500+ units in stock at a unit price of $32.50 USD (1000 units at $26.80 USD).
Recommended Next Step
Testing Recommendation: Replace the memory with an i.MX95 EVK board for testing (NXP free tool support). NXP provides free DDR verification services if needed (community.nxp.com).