I2C Rise/Fall time measurement points

[Danz1]

Hi, 

CH1 in the waveform below shows the rising edge of the I2C Clock signal. 

The I2C rise time of the IC is specified as 30%-70% of VCC.

In the waveform captured, is the rise time measured from 0.99V (=30% of Vcc) to 2.31V (=70% of Vcc)?

Since Vmin is at 0.517V. Should the rise time be measured from 1.352V (=0.517V+0.3[3.3V-0.517V]) to 2.465V (=0.517V+0.7[3.3V-0.517V])?  

Thanks.

Rgds

Danz

[AnNguyen952842]

Hi,

I am a newbie. when using oscilloscope to measure I2C signal ( fast mode plus) 

what sample rate I need use? 20 MS/s or higher like 500MS/s 

because i met one case that 

1. Using Scale 10us/div + sample rate lower than 200 MS/s then sometimes rise time fail ( > 120ns) both SDA/SCL

2. Using 10us/Div + 500MS/s -> get PASS result 

So what is correct ? how I can calculate sample rate

Thanks a lot !

[diazmarin09]

Hello Danz1,

I hope all is great with you. Thank you for using the NXP communities.

Could you please share the timing parameters of your device?

Usually, the 30% and 70% of VDD refers to logic levels, not timing.

Regards,

David

[Danz1]

Hi David,

I use the I2C specification as an example. The rise time and fall time is defined from 03Vdd to 0.7Vdd as indicated in the waveform. VIL and VIH are also defined as 0.3Vdd and 0.7Vdd respectively.

With reference to the captured waveform I posted earlier, should the rise/fall time measure between 1.352V to 2.465V or measure between 0.99V to 2.31V?

Rgds

Danz    

[diazmarin09 · Accepted solution]

Hello Danz1,

Once again, thank you for using the NXP communities.

Please accept my apologies for the delayed response.

Correct, the rise and fall time should be based on a valid logic level. I mean, I do recommend to measure such timing from 30% and 70% of the VDD.

I hope this information helps.

Regards,

David

[Danz1]

Hi David,

Noted. Thank you for your reply.

Rgds

Danz