How to enter the OFF state of the MMPF0100 PMIC?

[clemensterasa]

Hello,

we are using the MMPF0100 PMIC (MMPF0100F0AEP) to drive a i.MX6 Dual SoC board. Our design has a Li ION Accu (not connected to the LICELL pin) that is supposed a s backup supply for a limited time.

Our goal is to detect the loss of the power-line based supply to conduct some emergency actions and switch the PMIC into the OFF state to save battery power (for the wake-up logic).

Our plan is achieve this using the transition from ON to OFF holding the PWRON low for 4 seconds.

From the state diagram of the PF0100 Figure 8. State diagram (MMPF0100 Rev. 17.0, 1/2017)

PWRON = 0 held >= 4.0 sec
All SWxOMODE bits= 0
& PWRONRSTEN = 1
(PWRON_CFG = 1)

However the available  PF0100 ICs are all pre-programmed as level-triggerd PWRON (PWRON_CFG =0) and our design currently uses the level triggered PWRON to boot-up the SoC.

We now want to switch to the edge triggered mode PWRON_CFG=1 after boot-up.

Is it possible to configure the PWRON_CFG=1 bit dynamically without using fuses (or the TBB feature)?

How can we use the  "PWRON low for 4 seconds tuns the PMIC OFF" feature?

[clemensterasa]

I found a way to switch into level triggered PWRON config mode dynamically.

Following a simple sequence I used form a Linux Yocto shell (provided that the PMIC is connected to the first I2C port an dhas the address 0x08):

i2cset -f -y -r 0 0x08 0x7F 0x00 # Functional Page (0)
i2cset -f -y -r 0 0x08 0x1B 0x12 # PWRONRSTEN  
i2cset -f -y -r 0 0x08 0x7F 0x01 # Extended Page 1 
i2cset -f -y -r 0 0x08 0xE0 0x11 # PWRON_CFG1=LVLtrigger | SEQ_CLK_SPEED1 =2.5ms 
i2cset -f -y -r 0 0x08 0xE1 0x11 # PWRON_CFG2=LVLtrigger | SEQ_CLK_SPEED2 =2.5ms 
i2cset -f -y -r 0 0x08 0xE2 0x11 # PWRON_CFG3=LVLtrigger | SEQ_CLK_SPEED3 =2.5ms 
i2cset -f -y -r 0 0x08 0xE4 0x82 # TBB_POR & FUSE_POR1 
i2cset -f -y -r 0 0x08 0x7F 0x02 # Extended Page 2 
i2cset -f -y -r 0 0x08 0x88 0x00 # !OTP_SHDWN_EN  
i2cset -f -y -r 0 0x08 0x7F 0x01 # Extended Page 1 
i2cset -f -y -r 0 0x08 0x84 0xC0 # Reload: START & RL PWBRTN
sync

Now I can turn the PMIC to the OFF mode by holding the reset button (connected to the PWRON pin) for 4 seconds.

It comes back on by pressing the reset button again.

However the Datasheet states this feature is a "Test-Before-Buy" (TBB) feature.

1. Is it safe to use this in a productive environment?
2. What are the drawbacks of the TBB feature (besides the loss of the configuration on VIN fail)?

Edit: Corrected shell snippet

[reyes]

Hi,

Yes, it is possible to configure the PWRON_CFG=1 bit dynamically without using fuses (or the TBB feature), in order to  in order to use the  "PWRON low for 4 seconds tuns the PMIC OFF" feature, you will need to set the following configuration:

All PWRON_CFG bit = 1 (set as an edge sensitive input),

As an edge sensitive input, such as when connected to a mechanical switch, a falling edge turns on the part and if the switch is held low for greater than or equal to 4.0 seconds, the part turns off or enters sleep mode.

All SWxOMODE bit = 0 (any regulator whose SWxOMODE bit is set to “0” will be turned off),

RESTARTEN bit = 0 (setting this bit to zero should avoid to make an automatic restart after pressing the PWRON button low for more than 4 seconds),

PWRONRSTEN = 1  

This is how this configuration is done:

All PWRON_CFG bit = 1:

                PWRON_CFG1 bit 4 on Register 0xE0 (*Extended Page 1)

PWRON_CFG2 bit 4 on Register 0xE1 (*Extended Page 1)

PWRON_CFG3 bit 4 on Register 0xE2 (*Extended Page 1)

All SWxOMODE bit = 0: 

                SW1ABOMODE bit 5 on Register 0x23

SW1COMODE bit 5 on Register 0x31

SW2OMODE bit 5 on Register 0x38

SW3AOMODE bit 5 on Register 0x3F

SW3BOMODE bit 5 on Register 0x46

SW4OMODE bit 5 on Register 0x4D

PWRONRSTEN = 1:

                PWRONRSTEN bit 1 on Register 0x1B

RESTARTEN = 0:

                RESTARTEN bit 0 on Register 0x1B

Then, PWRON is held low for longer than 4.0 seconds.

*In order to enter to Extended Page 1, you first need to write 0x01 to the page register at address 0x7F.

Have a great day,
Jose

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[clemensterasa]

Hello Jose, thank you for your reply.

Unfortunately the process you described did not work.

No change in behavior of the PWRON pin can be detected.

I tried the following:

Setting "All PWRON_CFG bit = 1:":

i2cset -f -y -r 0 0x08 0x7F 0x01 # Extended Page 1 
i2cset -f -y -r 0 0x08 0xE0 0x11 # PWRON_CFG1=LVLtrigger | SEQ_CLK_SPEED1 =2.5ms 
i2cset -f -y -r 0 0x08 0xE1 0x11 # PWRON_CFG2=LVLtrigger | SEQ_CLK_SPEED2 =2.5ms 
i2cset -f -y -r 0 0x08 0xE2 0x11 # PWRON_CFG3=LVLtrigger | SEQ_CLK_SPEED3 =2.5ms 

Setting "All SWxOMODE bit = 0":

i2cset -f -y -r 0 0x08 0x7F 0x00 # Functional Page (0)
i2cset -f -y -r 0 0x08 0x23 0x08 # SW1ABOMODE := 0 | APS
i2cset -f -y -r 0 0x08 0x31 0x08 # SW1COMODE  := 0 | APS
i2cset -f -y -r 0 0x08 0x31 0x08 # SW2OMODE   := 0 | APS
i2cset -f -y -r 0 0x08 0x31 0x08 # SW3AOMODE  := 0 | APS
i2cset -f -y -r 0 0x08 0x31 0x08 # SW3BOMODE  := 0 | APS
i2cset -f -y -r 0 0x08 0x31 0x08 # SW4OMODE   := 0 | APS

Setting PWRONRSTEN = 1: and RESTARTEN = 0:

i2cset -f -y -r 0 0x08 0x7F 0x00 # Functional Page (0)
i2cset -f -y -r 0 0x08 0x1B 0x12 # STBYDLY := 1 | PWRONRSTEN | !RESTARTEN

Pressing the button connected to the PWRON in the PMIC resets instantly and the device boots up after release.

It seems that the some registers of the register set are only read on PWRON or via the TBB feature and not dynamically.

I currently think that the process described in http://cache.freescale.com/files/analog/doc/app_note/AN4536.pdf  

"2.4.3 OTP Register Reloading without Turn-on Event" needs to be followed to achieve what we are trying.

[reyes]

Yes, sorry, totally forgot to mention that, you need to enter into TBB mode before make the suggested register changes, otherwise you will not be able to write to the registers.

In order to enter into TBB mode, follow the instructions on the application note AN4536.

Take in mind that VDDOTP pin should be connected to GND during TBB mode.