Hi Freescale support,
I am working on the QorIQ T Series T4240. Could someone guide me on how to configure 3-way 4KB interleaving mode on U-boot?
My board has 3 memory controllers, each with 8GB.
I attempted to enable 3-way CS0_CS1 interleaving as shown below:
/* Enable DDR Interleaving */
pinfo->memctl_opts[i].ba_intlv_ctl = FSL_DDR_CS0_CS1;
pinfo->memctl_opts[i].memctl_interleaving = 1;
pinfo->memctl_opts[i].memctl_interleaving_mode = FSL_DDR_3WAY_4KB_INTERLEAVING;
temp_sdram_cfg = pinfo->fsl_ddr_config_reg[i].ddr_sdram_cfg;
However, I have been faced the u-boot crashed, it was due to the lawbar setting for 3-way 4K
https://github.com/nxp-qoriq/u-boot/blob/lf_v2024.04/drivers/ddr/fsl/main.c #line 823
case FSL_DDR_4WAY_8KB_INTERLEAVING:
law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
if (i == 0)
fsl_ddr_set_lawbar(
&pinfo->common_timing_params[i],
law_memctl, i);
/* place holder for future 4-way interleaving */
break;
I don't understand why fsl_ddr_set_lawbar is used for Memory Controller 1 only. It should work if I remove the "if (i==0)" condition, as it would mean that fsl_ddr_set_lawbar will be set for every Memory Controller.
Could anyone please give me any ideas how to resolve this problem.
Thank you
