GD3162 gate driver WDOG fault

[Akshat_VE02376]

Hi NXP,
I have some concerns regarding WDOG fault which is causing some issues in our project.
We have observed that it occurs for the Power-up sequence in which LV domain is powered up prior to the HV domain. But when the HV domain is powered up first then the fault doesn't occur. Is there any way to clear the fault in the time? Suppose when Low voltage domain is powered up first and then the HV domain. Then for the instance of time in which there was no power being supplied to the HV domain, the WDOG fault occurs due to inactive HV die. But once HV is active, in that case can the WDOG fault be cleared? And another doubt is regarding the RESET bit of MODE 2 register. Does this reset bit also clears the latched fault? In the data sheet it is mentioned that INTB will be low. Can you verify this that why INTB will be low? Is it because PWM will be off? Once RESET is done using this bit then will we be able to do the configurations again and will the gate driver's output PWM will be re-enabled automatically in the same power cycle?

[TomasVaverka]

Hi,

All faults can be cleared by writing a "1" to the corresponding bit in the associated STATUSx register. To clear the watchdog fault, make sure both HV and LV sides are properly powered, then write the WDOG_FLT bit to 1 in the STATUS2 register. See also section 12.4 of the datasheet.

At 1st powerup, if LV side is powered before HV side, a WDOG_FLT will appear, until HV side is powered. At this point, the WDOG_FLT will automatically be cleared. Note that this only happens once, i.e. if the HV side then experiences a POR event, the WDOG_FLT will be latched even when power is restored.

Regarding RESET, the following sequence should be observed:

1) enter configuration mode by setting the CONFIG_EN bit to 1 in the MODE2 register. PWM operation will be disabled, INTB stays high.

2) Write the RESET bit to 1 in the MODE2 register. INTB will go low and all registers will be reset to their default value, PWM operation is still disabled.

3) Write RESET bit to 0. INTB will go back high, and PWM operation is allowed. The configuration registers can be written at this point.

BRs, Tomas

[Akshat_VE02376]

Thanks for the quick clarification. One follow-up question would be, if during initialization I clear all the bits in Status 1 and 2 registers by writing 1 to all bits of status registers, then only the faults which are not actually present will be cleared and remaining will still be latched in status registers right?

[TomasVaverka]

Hi,

Yes, if you write 1 to all bits of the Status 1 and Status 2 registers during initialization, only the faults that are no longer present will be cleared, while any active faults will remain latched in the status registers.

BRs, Tomas