GD3162 Daisy Chain

[Akshat_VE02376]

Hi NXP,
This is regarding the Daisy Chain configuration of gate drivers in our project. You can refer to the diagram which I've shared for understanding the connections. The chip selects for higher 3 and lower 3 gate drivers are different but the MOSI line going to RH and RL gate drivers is the same MOSI line coming from the micro. Similarly MISO line from BH and BL is connected to the single pin of micro. The issue which I'm facing is, when I'm trying to write the same data to all 6 gate drivers, then I'm succeeding but when I'm trying to configure different data for top 3 and different data for bottom 3 gate drivers in that case data is getting corrupted or wrongly written to some registers. Is it due to the shared MOSI and MISO line? What can be the solution for this issue? Is it possible to configure high and low side gate drivers with separate data? For some registers, it seems to work perfectly but this is not the case for all the registers. Although data is being consistent for higher 3 and lower 3( separately.) Please do respond!

[RafaR]

Hi Akshat

I'm working on your other case, "GD3162 SPIERR." I sent you feedback two days ago. Could you please confirm if that issue has been resolved?

I've already contacted AE with more experience with this device who is fully available to help us resolve these issues, I just want to confirm if the other issue is resolved so we can continue with this one.

I will be waiting for your response

Have a great day and best of luck.

[Akshat_VE02376]

Hi Rafar,
No the issue is not yet resolved.
SPIERR is also occurring when I'm trying to write different data to the lower 3 gate drivers. Please do confirm that in the given design is it really possible to configure all the registers of upper 3 or lower 3 gate drivers separately

[RafaR]

Hi Akshat

The AE confirms your connection and gave me several comments for justification and explanation.

Yes, your connection looks correct. When using this configuration, only one signal (CSB_L or CSB_H) must be low at once. The frame should contain 24*3 bits per CSB low pulse, containing data for device R/Y/L. There is no issue in sharing MOSI & MISO lines. MISO of gate drivers which have CSB line high will be in high impedance mode, meaning the other daisy-chain will be able to assert MOSI line without any conflict. And any pulses on MOSI/SCLK will be ignored by the gate drivers when CSB is high.

The AE insists that you respond to his last request "GD3162 SPIERR." because this information is more detailed to find the problem.

“To further debug this issue, as asked previously, please provide waveforms of the complete SPI frame, including INTB line to check when the SPIERR occurs. Please also provide a reference frame where SPI si working (i.e. when you write identical data).”

I will be waiting for your response

Have a great day and best of luck.

[Akshat_VE02376 · Accepted solution]

Hi Rafar,
I did several changes and the issue was resolved:
I configured all 6 gate drivers and then I overwrote the required configuration to the lower 3 gate drivers and introduced 100 microseconds of delay after writing each register for all 3 gate drivers. This way I was able to configure lower 3 with a separate configuration and also observed that the SPIERR was resolved.
SPIERR was occurring in the previous implementation where I didn't give any delay after writing to one register and I was doing the write operation only for RL and YL gate drivers and not BL (for BL I sent a dummy read frame in Chain).

[RafaR]

Hello Akshat

Ooh, sounds great, congratulations.

Thank you for letting us know about your implementation, your procedure for solving the SPIERR was interesting.

Have a great day and best of luck.

[Akshat_VE02376]

Hi NXP, 
This is again regarding SPIERR.
After configuration of GD registers...I'm not facing SPIERR until PWM is enabled...Once We're enabling PWM to GD in that case SPIERR is triggering sporadically in any of the gate drivers (for 3 phase PMSM motor application). Earlier I phased SPIERR while I was overwriting to the GD registers which was resolved after I gave 50us of delay. But now it triggers only when we enable PWM. Please look to this issue as soon as possible and clarify that whether we need to look into SW or HW