FRWYLS1046A DDR configuration parameters

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FRWYLS1046A DDR configuration parameters

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rashmikj
Contributor III
Hi, Can anybody share DDR parameters used for initialization of FRWY Kit as captured by QCVS DDR tool?
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Pavel
NXP Employee
NXP Employee

See attached file. This file is available in NXP LSDK2012 or LSDK 2004 Linux BSP.

Use the following paths:

/packages/firmware/atf/plat/nxp/soc-ls1046/ls1046afrwy

and

/packages/firmware/atf/plat/nxp/drivers/ddr/fsl-mmdc

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rashmikj
Contributor III

What should be DQ Mapping ??  I have connected discrete DRAM and mapped DQ0 to DQ63 to Data pins of DRAM in 1:1 fashion. should it be DQ_0_3 is 0x00 and DQ_4_7 is 0x21 or should it be DQ_0_3 is 0x00 and DQ_4_7 is 0x00. I have mapped DQ(0:7) to DQ(0:7) data lines of DRAM.

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Pavel
NXP Employee
NXP Employee
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