FRDM33772CSPIEVB Battery cell controller

[hajianik]

Hi ,

I need your expertise. I'm trying to talk to FRDM33772CSPIEVB (to be used with BATT-6EMULATOR). I connected my Master SPI board which is a S32K310 eval board to the BCC SLAVE eval board(FRDM33772CSPIEVB) by connecting the SPI signals via  a bread board together, MOSI->MOSI, CS-CS, CLK-CLK, Miso-MISO. There's also a reset signal out from Master to the reset input of the slave board and grounds are connected . Some pictures from the set up are attached. Also attached is a Beagle SPI traffic  LOG that shows how the SPI is set up(initialization). I also send a reset pulse to BCC for 500us.We also checked

We also check the eval board (Vcom, SPI enabled ,Reset,…….)They are ok.

what I see: is no response on the MISO TO WHAT I SEND on MOSI..

THE LIST OF SEVEN PACKETS USED IN INITIALIZING AND SETUP ARE AS FOLLOWS:

1) Assign Address: BCCSPI_TxReg( 1, BCC_REG__SYS_CFG1, bcc_spi_regs[ BCC_REG__SYS_CFG1 ], &rx_data_u16 ); WHERE bcc_spi_regs[ BCC_REG__SYS_CFG1 ] = 0x3881u | 0x0010u.

THE SECOND IS :ASSIGN SEEDS

bcc_spi_regs[ BCC_REG__INIT ] = 0x0001;

2)BCCSPI_TxReg( BCC_CLUSTER_ID__UNASSIGNED, BCC_REG__INIT, bcc_spi_regs[ BCC_REG__INIT ], &rx_data_u16 );

   Configure the acquisition process

    bcc_spi_regs[ BCC_REG__SYS_CFG1 ] = cfg1;0X3881

    bcc_spi_regs[ BCC_REG__SYS_CFG2 ] = cfg2; 0X0030

   3) BCCSPI_TxReg( BCC_CLUSTER_ID__ASSIGNED, BCC_REG__SYS_CFG1, bcc_spi_regs[ BCC_REG__SYS_CFG1 ], &u16RxData );

   4) BCCSPI_TxReg( BCC_CLUSTER_ID__ASSIGNED, BCC_REG__SYS_CFG2, bcc_spi_regs[ BCC_REG__SYS_CFG2 ], &u16RxData );

   bcc_spi_regs[ BCC_REG__SYS_CFG1 ] = 0x3881 | 0x0200;

   5) BCCSPI_TxReg( BCC_CLUSTER_ID__ASSIGNED, BCC_REG__SYS_CFG1, bcc_spi_regs[ BCC_REG__SYS_CFG1 ], &rx_data_u16 );// EN CURRENT MEASURMENT

START ACQ PROCESS

bcc_spi_regs[ BCC_REG__ADC_CFG ] =  0x042A | 0X0800;

  6)  BCCSPI_TxReg( BCC_CLUSTER_ID__ASSIGNED, BCC_REG__ADC_CFG, bcc_spi_regs[ BCC_REG__ADC_CFG ], &u16RxData );

#if ( BCC_CHIP_VER_3_0 == 1 )

    u16RxData = 0;

    bcc_spi_regs[ BCC_REG__ADC2_OFFSET_COMP ] = 0XC000;

  7)  BCCSPI_TxReg( BCC_CLUSTER_ID__ASSIGNED, BCC_REG__ADC2_OFFSET_COMP, bcc_spi_regs[ BCC_REG__ADC2_OFFSET_COMP ], &u16RxData );

NOT GETTING ANY RESPONSE( 0) TO THESE PACKETS.

Please shed some light on this.

Regards,

Koorosh Hajiani

[hajianik]

Hi Josef,

Thank you for your response.

In below screen shot  the channel 1( Brown) is the clock  and channel 4 (yellows) the MOSI .  as you can see by the red vertical line , lines up with the trailing edge of the clk and the Mosi( rising edge)

[hajianik]

Hi Josef,

Thank you for your response.

In below screen shot  the channel 1( Brown) is the clock  and channel 4 (yellows) the MOSI .  as you can see by the red vertical line , lines up with the trailing edge of the clk and the Mosi( rising edge)

Even IF I go with phase1 does not change anything I still get a zero response to all my write and read requests.

CAN YOU PLEASE  ANSWER A VERY SIMPLE QUESTION RATHER THAN REFER ME TO DATASHEETS. The other day you mentioned my data for assigning CID is wrong and I asked you( with detail description of the format of the packet ) what is in error? YOU DID NOT ANSWER THAT and rather ask me about a more focused view of the SPI transfers ,which I'm providing in this post. I will ask this second time and please answer to this specific question and don't send me on a goose chase. to assign a CID , I'm sending the following packet , if this is in error ,please indicate the correct packets to be sent:

0x01, 0x01,,0x01,0x00,0x02,0x28

Again  from the left :  the 1st 2 bytes are the data(assigned CID) , 3rd byte is the address, 4th is the unassigned CID,5th is command byte(write), 6th is the CRC.

I've been working with lots of your colleagues and in a situation like this , they just do a simple test on their own I'm not the one to tell you what to do, but at this point ,it seems to be the best solution.

Thanks,

Koorosh Hajiani

[hajianik · Accepted solution]

according to the picture below from the  MC3772C.

My SPI driver does not meet the condition of the clk input low before the CSB is asserted.

Thanks,

[JozefKozon]

Hi Koorosh, 

the recommended MCU board for the FRDM33772CSPEVB is S32K144EVB. Both boards are hardware/software compatible. Please consider purchasing the recommended board. You can directly mount the FRDM33772CSPEVB on top of the S32K144EVB and use the GUI, and software on the FRDM33772CSPEVB page. 

With Best Regards,

Jozef

[hajianik]

Hi, 

Thanks for your response.

Kind of disappointed at your response. The fact that s32k144 is companion device for this board has nothing to do with this situation.

We can drive this cell controller (slave device)using any master assuming all SPI data lines, reset, and GND's are connected, correct? It shouldn't matter that we are using ANY master device including the S32K31XEVB-Q100 as opposed to using an S32K144.

Respectfully, this is dodging my question. tell me why I'm getting 0 value on the Miso line.?

I send you a lot of information including the SPI log (7 messages) to  configure the cell controller.

I'd request to escalate this to someone who has expertise in this area. 

Regards,

Koorosh Hajiani

[JozefKozon]

Hi Koorosh, 

I apologize for my inconsistency. Yes you can use any master you want to write and read from the MC33772C registers. Please share a scope from the SPI lines. I would like to check if you have correct SPI mode. Please refer to the Figure 20. in the MC33772C datasheet. The CPOL should be 1, the SCLK high on Idle and the CPHA should be 0. Data changed on SCLK rising edge and sampled on SCLK falling edge. 

You have send the correct 48bit format, but with incorrect data. At first you need to initialize the MC33772C with a new Cluster ID. You need to send a write command with a default CID=0b00 0000, and assign a new CID. Please refer to the sections 11.2 and 10.4.2 in the MC33772C datasheet.

With Best Regards,

Jozef

[hajianik]

Hi Josef,

Thank you for your response.

the first screen capture below shows the SPI CONFIGURATION. 

CLK:IDEAL HIGH

Phase 0 trailing edge. actually I tried leading edge and did not make any differences

the screen below shows scope capture:

Where brown is the clk , Red CS, ORANGE MISO, Yellow the MOSI. I know the clk is wearied but in my past experience with NXP drivers, it's been like this. anyways the clk appears normal during the cs assertion at a frequency of 4mhz. 

You also mentioned the initialization process:

Please look at fifth packet on MOSI , which reads:

0x01,0x01,0x01,0x00,x02, 0x28

I failed to see what is wrong with this packet.

the 1st 2 bytes (0x01,0x01) are configuration data for the init register. the 1st byte (0x01)is: Stop forwarding and response on single side and the 2nd byte is 0x01 which is cluster id of 0x01.

3rd byte is the init register address 0x01.

4th byte is 0x00 which assigns a default cluster id ( bit 16 to 23)of 0x00

the 5th is command field of 0b10

6th byte is CRC.

Will you please point out the error data in this packet.

Regard,

Koorosh Hajiani

[JozefKozon]

Hi Koorosh,

please confirm, that you have the MC33772C full datasheet. When initializing the new MC3377xx, you need to follow the format in the section 10.1. in the MC33772C datasheet. Please share more focused view of the SPI waveforms. I need to check the timings of the SCLK and MOSI. If the CPHA is indeed 0. 

Please note: "Unlike the read command, for which MC33772C responds with data, the write command
does not generate any response."

With Best Regards,

Jozef