Tank you, is the same documentation I have just found. But I think I'm making something wrong, I can't make the desired signal. This is my code, do you see something wrong? MPC5554 is running at 80 MHz. I need 135ms LOW and 30ms HIGH as reported in the previous post
void initEMIOS(void)
{
EMIOS.MCR.B.GPREN = 0; // Enable eMIOS clock
EMIOS.MCR.B.GPRE= 79; // Divide 80 MHz sysclk by 79+1 = 80 for 1MHz eMIOS clk
EMIOS.MCR.B.ETB = 0; // External time base is disabled; Ch 23 drives ctr bus A
EMIOS.MCR.B.GTBE = 1; // Enable global time base
EMIOS.MCR.B.FRZ = 0; // Enable stopping channels when in debug mode
EMIOS.MCR.B.GPREN = 1; // Enable eMIOS clock
}
void initEMIOSch23(void)
{ // EMIOS CH 23: Modulus Up Counter
EMIOS.CH[23].CADR.R = 999; // Period will be 999+1 = 1000 clocks (1 msec)
EMIOS.CH[23].CCR.B.MODE = 0x10;// MPC555x: Modulus Counter (MC)
EMIOS.CH[23].CCR.B.BSL = 0x3; // Use internal counter
EMIOS.CH[23].CCR.B.UCPRE=0; // Set channel prescaler to divide by 1
EMIOS.CH[23].CCR.B.FEN = 0;
EMIOS.CH[23].CCR.B.FREN = 0; // Freeze channel counting when in debug mode
EMIOS.CH[23].CCR.B.UCPREN = 1; // Enable prescaler; uses default divide by 1
}
void initEMIOSch14(void)
{
// EMIOS CH 14: Output Pulse Width Modulation
EMIOS.CH[14].CADR.R = 130;
EMIOS.CH[14].CBDR.R = 165;
EMIOS.CH[14].CCR.B.BSL = 0x0; // Use counter bus A (default)
EMIOS.CH[14].CCR.B.EDPOL = 1; //Polarity-leading edge sets output/trailing clears
EMIOS.CH[14].CCR.B.MODE = 0x20; // MPC555x: Mode is OPWM
SIU.PCR[203].B.PA = 1;
SIU.PCR[203].B.OBE = 0;
SIU.PCR[203].B.IBE = 0;
SIU.PCR[203].B.ODE = 0;
SIU.PCR[203].B.HYS = 0;
SIU.PCR[203].B.SRC = 0;
SIU.PCR[203].B.WPE = 0;
SIU.PCR[203].B.WPS = 0;
}
