Erata SJA1110

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Erata SJA1110

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Debelak
Contributor I

Hello,

We are using the SJA1110 in a project.
Unfortunately, the design was implemented before the SJA1110 errata sheet was published. We disregard the PowerUp sequencing, in our case the VDD11 is booted with the VDD33.

Erata point ES_SJA1110: 100BASE-TX power-up sequence
Contrary to the assertion in section 12.3 of the data sheet that no special sequencing is
needed during supply ramp-up, the SJA1110 must follow a defined power-up sequence
when the 100BASE-TX port is used.
If VDDA33_100BTX is switched on before VDD11_CORE, the performance of the
100BASE-TX port may be degraded (higher BER).

Can you specify the effect on the 100Base-TX interface in more detail?
Functional restriction of the interface, ....

Best regards and thank you
Albrecht

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3 Replies

162 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

lets continue with a Support Case I created for this. You have been notified.

Thanks.

BR, Petr

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115 Views
Debelak
Contributor I

Hello Peter,

Do you have any news about my question?

I urgently need an answer to be able to assess the risk.

Thank you

Albrecht Debelak

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107 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

I replied via Case in fact, but have no info still...
 
unfortunately no feedback is received from R&D. AE engineer re-triggered R&D again.
 
BR, Petr
 
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