Does TJA1052IT/5Y Transceiver has input protection diode between TX pin and the VDD/RX pin

[Vishal_Pandey]

Hi, 

I am using #TJA1052IT/5Y in my project and my project demands sleep mode. For sleep mode (Standby mode of CAN - ignore this in discussion) I am using a Load switch which is connected on VDD1 line of the CAN transceiver and nothing on the VDD2 (VDD2 is always powered). 

According to datasheet  When VDD1 is < V(ud) or unpowered, bus should be in dominant mode but it is not the case, CAN messages sneak through and lands on the bus. VDD1 voltage in this condition was 3.6V approx.  

To debug issue, I had done CAN initialization and refrained from sending any msgs and checked the voltages -  CAN TX is recessive (1)  and Vdd1 and RX is 3.6V. Why Vdd1 is 3.6V ? WHen the code is erased from microcontroller flash - CAN TX, Vdd1 and RX is 0.

 Does TJA1052IT/5Y Transceiver has input protection diode connected between TX pin and the VDD/RX pin  or is there any power sequencing which is violated? 

However in next version I will make Vdd2  less than threshold and make it disconnect from the buss (mentioned in datasheet). 

[guoweisun]

There is no diode between TX/RX,for the power up/down sequence please see below:

If the TJA1052i is used in a HS-CAN network that supports remote bus wake-up, the
power- down sequence of the supplies must be managed properly to avoid a dominant
pulse on the CAN bus.

As soon as the undervoltage threshold of VDD1 is passed during ramp down the
oscillation is also stopped and therefore the CAN bus is driven dominant until the TXD
dominant time-out time overflows and the TJA1052i releases the CAN bus again.

In order to avoid the dominant pulse VDD2 should pass the minimum undervoltage threshold (Vuvd(stb)(VDD2)(min)) before VDD1 falls below its maximum undervoltage detection threshold (Vuvd(VDD1)(max)).
Power-up sequencing can happen in any order. Note, that the isolator takes maximum 500 μs before the modulation is stable (see data sheet tstartup). The start-up time is the time from the application of power to valid data at the output.

[Vishal_Pandey]

Hi,

Thanks for sharing the power sequencing, I am facing problem where according to the table 5 in datasheet and in the fig. shared by you as well  where "CAN is dominant until timeout" when VDD1 is detected under-voltage, this is not happening in my case(VDD1 line is already disconnected from the supply 5V) .  While debugging I found that VDD1 has not went below the  min Vud detection (2.7V) but was at 3.6V. Further when I disconnected Tx pin from the CAN TXCR, VDD1 is now unpowered. 

With TX given as 1(4.9 V)  VDD1 is not reaching the under voltage and which is still causing few CAN msgs put on the BUS.

[guoweisun]

Can you share with your schematic?

[Vishal_Pandey]

Hi, 

Attaching the schematic for your reference.