Connection method of PTN5150 on OM13588

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Connection method of PTN5150 on OM13588

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mitsugu_imai
Contributor I

Hi I am Mitsu,

I'm trying to test for PTN5150 using EV-Kit OM13588.

And I want to connect using I2C.

However, it seems that I can not connect PTN5150  using I2C.

According to the schematics(sch_29705.pdf) ,

there are no connection from I2C pin.

It will be able to control the PTN5150 on this board using I2C? 

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mitsugu_imai
Contributor I

PTN5150A.jpgHi Tomas,

Thank you for the good advice.

I understood how to connetc I2C Line.

It will be possible to connect from PTN5150A to Jumper connecter?

According to schematic of PTN5150A, there are No connection from U9.

#7 as SDA and #8 as SCL are routed to 'x' .

How do I think it?

Best Regards,

Mitsugu

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TomasVaverka
NXP TechSupport
NXP TechSupport

Hi Mitsugu,

You are right, only PTN5110 I2C pins are routed to the connectors, I do apologize for overlooking it.

You may need to use another board - the OM13584:

pastedImage_1.png

Best regards,

Tomas

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anton_curaj
Contributor I

Dear Tomas,

I have read your response above and would like to ask few questions about our design with the PTN5150HX inside.

It is designed to run legacy OTG link over USB Type-C connector. We've opted to start our design without support of the (not readily) available evaluation board (OM13584). 

PTN5150HX version with Pin 11 = ENB Active Low is our choice, but PTN5150HHX with Pin 11 = EN Active High would be equally suitable as well if this is the only difference.

 

However, datasheets of both parts on page 4 differ in another (important?) detail related to connection of the VBUS_DET pin to VBUS line.

- PTN5150HX (and also PTN5150AHX) recommends (prescribes?): "Directly tie to VBUS of the USB Type-C receptacle.".

- PTN5150HHX on the other side recommends (prescribes?): "One 1 MOhm +/-1 % external resistor required between system Vbus and VBUS_DET pin.".

 

1. VBUS_DET pin has 28V max tolerance in both cases, so why is the 1M series resistor required for one version but not for other two versions? 

 

2. These are actually two different conditions for (almost?) the same silicon. Could you please confirm there is a real internal difference on the VBUS_DET pin for different chip versions and explain its behaviour in both cases?

 

3. What is the internal structure of this pin for different chip versions (impedance, leakage, threshold, hysteresis,...) please?

 

4. We would like to operate PTN5150xHX in DRP and non-I2C mode.   

What is the internal timing / switching between DFP and UFP modes, detection of VBUS_DET and CCx pins status (voltage level). What is the initial mode after start up?

 

5. Could you please provide state (and timing) diagram and transition between subsequent connection events?

Is status of the ID and CON_DET pins based purely on static voltage levels on the CCx and VBUS_DET pins, or is there some dependency (state machine) on a previous connection state? Could you please provide deeper application details that are not covered in datasheet?

6. What is the internal structure of the ADDR/CON_DET and PORT pins? Is there some high-ohmic divider to set a pin voltage to mid of VDD in case no external pull-ups / pull-downs are used (floating pins)? Is the floating state equally effective (fully equivalent) to use of an external divider 10k pull-down / 10k pull-up?

I'm providing you a detailed schematic of our proposed solution for your kind review and potential approval of its intended operation as described below. Here are few related points:

- VBUS link is not required to supply internal electronics if external host is attached (U2 load switch must remain OFF)

- PORT pin, set to mid voltage (with both R4 and R6 assembled, or both resistors Not Fitted), selects DRP mode

- ADDR/CON_DET pin, set to mid voltage with R10 and R5 (at chip start up), selects the GPIO mode for U1 chip

- ADDR/CON_DET pin is used to drive the EN pin of the U2 load switch HIGH only in PTN5150's DFP mode (attached USB stick), when ID = LOW  &  ADD/CON_DET = HIGH. P-channel MOSFET Q1 is switched ON by LOW state on its gate (pin 1), when ID = LOW, against HIGH state of ADD/CON_DET on the Q1's source (pin 2).

- R12 provides bus discharge path

- Is the series (protection?) resistor R11 required for PTN5150HX chip (our choice)?

- Is C6 necessary close to VBUS_DET pin for filtering possible VBUS glitches?

- Is bulk capacitance C5 necessary for VBUS filtering or is it required for proper detection of the VBUS voltage ramping up or down?

 

Looking forward to your support in advance.

 

Kind greetings,

Anton

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mitsugu_imai
Contributor I

Hi Tomas

Sounds good,  I am going to use OM13584 according to your advice!

Thanks for everything !!

Best regards,

Mitsugu

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TomasVaverka
NXP TechSupport
NXP TechSupport

Hi Mitsugu,

I2C_SCL and I2C_SDA are routed to J10 as shown in the schematic:  

pastedImage_1.png

They are also accessible on J11/J12 and Arduino headers:

pastedImage_2.png

pastedImage_3.png

Hope it helps!

Best regards,

Tomas

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