CAN-Transceiver TJA1051 - necessary waittime from "setting silent Pin Low" to "send a dominate Bit"?

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CAN-Transceiver TJA1051 - necessary waittime from "setting silent Pin Low" to "send a dominate Bit"?

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allgemi1
Contributor I

Hello,

The CAN-Transceiver TJA1051 can be set into "silent Mode".

A HIGH level on pin S selects Silent mode -> the transmitter is disabled -> releasing the bus pins to recessive state.

According to Application Hint AH1014 - Rev.01.40 - 27 April 2015:

"Chapter 3.3.2 Bus dominant clamping prevention at entering Normal Mode
Before transmitting the first dominant bit to the bus in Normal Mode the TXD pin once
needs to be set HIGH in order to prevent a transceiver initially clamping the entire bus
when starting up with not well defined TXD port setting of the microcontroller."

Now my question:

How low do I have to wait from setting pin S to LOW (leaving silent mode > entering normal mode), till I can send a dominant Bit?

Thanks for your effort and your respones

Michael Allgeier

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3 Replies

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TomasVaverka
NXP TechSupport
NXP TechSupport

Hello Michael,

 

The intention is to avoid TXD dominant time out when TXD was set to dominant for long time 0.5ms to 5ms.

So, if counter for TXD dominant time out was reset by setting TXD to recessive once, the dominant time out doesnt happen after entering Normal mode.

Time for keeping TXD in Recessive is not so critical.

So, while silent mode is selected by S=High, TXD should be set to Recessive.

Dominant can be selected after S is set to Low.

 

Best regards,

Tomas

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allgemi1
Contributor I

Hello Tomas Vaverka,
thank you for your response.
 
According to your response:
"So, while silent mode is selected by S=High, TXD should be set to Recessive.
Dominant can be selected after S is set to Low."
there is no wait time necessary after setting S=Low before transmitting the first dominant Bit.
 
However, following behavior occurs:
- silent mode is active (S=High),  TXD is set to Recessive (logical 1 / High)
- normal mode gets entered by setting S=Low
-> if I transmit a dominant Bit (TXD = logical 0 / Low) within the first 1.5µsec after setting S=Low, CAN-L / CAN-H stay "rezessive" (get not driven "dominant").
 
Within the Datasheet no minimum wait Time can be found. However, within Application Hint AH1014 - Rev.01.40 - 27 April 2015 following entry can be found:
 
"Chapter 3.3.2 Bus dominant clamping prevention at entering Normal Mode
Before transmitting the first dominant bit to the bus in Normal Mode the TXD pin once
needs to be set HIGH in order to prevent a transceiver initially clamping the entire bus
when starting up with not well defined TXD port setting of the microcontroller."
 
I would like to know:
How long is the minimum wait time which have to be wait till a dominant Bit can be transmitted after entering Normal Mode?
 
Thanks for your effort, support and your response.
Michael Allgeier
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TomasVaverka
NXP TechSupport
NXP TechSupport

Hello Michael,

 

Please see below the answer I received on this from our expert:

The longest mode change time is less than 50 µs. Thus it is recommended to wait these 50 µs to ensure a proper functionality. Note that after entering Normal mode and before starting transmission of the first dominant bit (start of frame) the TXD pin shall be recessive (TXD = HIGH).

 

Best regards,

Tomas

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