Hi,
I'm not getting anywhere with looking at this.
I have tried changing the crystal on my board to 8MHz but it made no difference (apart from the obvious connection speed changes).
Tried Vcc=3.3V and 5V
Looking at the log in detail it appears to fail several times with the detect chip before succeeding. It then fails to connect for the verify. When it fails it appears to be detecting a communication speed of about 40MHz (80MHz bus clock assuming no changes to BDMSTS.CLKSW) which is out of range for the chip.
From log
444:Speed = 4000 kHz (1920 ticks, sync=32.0 us)
530:Speed = 39385 kHz (195 ticks, sync=3.2 us)
810:Speed = 4000 kHz (1920 ticks, sync=32.0 us)
896:Speed = 39385 kHz (195 ticks, sync=3.2 us)
1259:Speed = 4000 kHz (1920 ticks, sync=32.0 us)
1546:Speed = 4000 kHz (1920 ticks, sync=32.0 us)
1753:Speed = 3996 kHz (1922 ticks, sync=32.0 us)
About the only reason I can think for this happening is that the device is being reset during communication.
Is is possible that there is an external watchdog on the reset pin?
Sorry but I can't think of anything to try at this stage.
Could you give a description of what exactly you are doing? Are you replacing a chip in the board or cloning a module?
bye