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NXP Tech Blog

andrewmeyerbti
Contributor III

The internal clock frequency of Kinetis chips varies due to manufacturing tolerances. A trim value is programmed into the chips to compensate for this variance and make the slow bus frequency uniform between chips.

For some inexplicable reason, this trim value is not active during debug mode. This makes developing serial and CAN applications very difficult, as the baud rates which are set are not the baud rates which are achieved. To make matters worse, if I understand the documentation correctly, the baud rate in debug mode is different from the baud rate in normal mode.

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