I need to know what the void criteria is for soldering the MC06XS4200FK to a printed circuit board.

[glenn_varnon]

Currently, we are using the MC06XS4200FK High Side Switch in several of our new designs. I have been seeing some soldering anomalies on the HS0 and HS1 pins in which there is no visible solder. I am currently getting some x-rays of the device as it is soldered to the PCA. What I need though is the pass fail criteria for how much solder voiding I can have on the device pins.

IPC-A-610 indicates the following: "Thermal plane void criteria shall be established between the Manufacturer and the User".

IPC doesn't really give me any criteria about voiding on this bottom terminated component. I did look at AN2467 which is an application note on the Power quad flat no-lead package (PQFN). Again though, it gives me what a good solder joint should be, but no voiding criteria. So, I need to understand how to figure this out. Can anyone help me.

[glenn_varnon]

Well the person who designed this chip must have had some idea as to how to size the pin and to what tolerance to and  including overhead there must have been in order for the chip to maintain its performance. I guess my question is, how much connection can you loose before it impacts the limits set by the datasheet?

[TomasVaverka]

Hi Glenn,

I am afraid we cannot help on that, there are not any void criteria we could provide. 

Our application note is intended to give guidelines at PCB layout level to maximize the soldering quality.

Best regards,

Tomas

[glenn_varnon]

The designer of this chip must have had an idea as to how big the pad was and how bad of a solder connection you can have and still be functional. The designer chose this package type for a reason. The designer must have also done some calculations on the devices heat transfer qualities and what the minimum requirements might be for the device.

Glenn Varnon

MFG Engineer | TechnipFMC Schilling Robotics

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[TomasVaverka]

Hi Glen,

Apologies for the delay in getting back to you, I am still waiting for feedback from our application engineer who is in charge of this IC. I will definitely update this thread as soon as I get it.

Best regards,

Tomas

[glenn_varnon]

Thanks Tomas. I wasn’t sure if you were working on it or not. Let me know when you get some data.

Glenn Varnon

MFG Engineer | TechnipFMC Schilling Robotics

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[TomasVaverka]

Hi Glen,

Please find below the answer I received from the application engineer.

The percentage of void acceptance is application dependent. Depends on the RthJA targeted, the capability of the board to dissipate heat and ambient temperature. The void rate is more critical on the main flag where the power die is located (and btw. where the heat has to be dissipated).

The void rate on HS0 & HS1 is dependent on the current targeted to flow through those pins. It is up to customer to assess his void level according to its internal constraints.

Best regards,

Tomas

[glenn_varnon]

Tomas,

I think I have found the answer that I’ve been looking for.

I found a good guide for solder acceptability for this device. I looked in IPC-7093 titled Design and Assembly Process Implementation for Bottom Termination Components (March 2011). On page 75 in section 7.6.1 (“Voids in BTC Solder Joints), it talks about what kind of performance that some manufacturers shoot for in a good stencil design. The design tries to achieve 50 to 60% paste coverage on the pads. The intent is to have 50% coverage of the thermal pad. Note, this is with a pad design that has no via’s in the pads area’s and the pad areas are not segmented. This is much like the pad design and the stencil design you have in your datasheet.

Table 7-5 on page 76 compares the variations pad design and stencil design to show what the potential voiding might be. For example, if you have an unsegmented stencil design and you have no via’s on the pads, there is a 50% potential voiding that can occur on that pad. If you add a via to that pad, the potential void could be as high as 70%. If you cap that via, you can have a potential void of up to 35%.

So the document gives you at least some sort of guide as to what might be normal outcomes in the solder process and compares the various improvements of pad and stencil design. IPC-7093 also goes over how to improve coverage just like your AN2467 application notes does.

Again, there is the disclaimer that yes, you need to qualify the design and process to see if that coverage meets your application requirement. At least though, it gives you some guidance as to what kind of output you can expect in a solder process for this package design.

Glenn Varnon

MFG Engineer | TechnipFMC Schilling Robotics

P +1 530-747-2735

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[glenn_varnon]

Tomas,

In application note AN2467 section 7.2 “Solder joint reliability results”, it conveys that NXP experimentally gathers board-level data on reliability. It says that I can request the results of these experiments. I would like to request the solder reliability results for this package.

You would think that solder reliability would have come into play in deciding as to whether or not to use this package for this design in the first place. The datasheet describes all of the maximum parameters of the chip to and including environmental temperature, maximum current, voltage and so on. You do give “guidelines” for what the copper, silk screen and solder paste stencil should look like in the datasheet. For chip to have met all of your maximum requirements outlined in the datasheet, there must have been some guideline for how much of a solder connection was needed for the component to qualify for those requirements set in the datasheet.

Glenn Varnon

MFG Engineer | TechnipFMC Schilling Robotics

P +1 530-747-2735

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[glenn_varnon]

Tomas,

I have not heard from you in a while. Are you working this issue?

Glenn Varnon

MFG Engineer | TechnipFMC Schilling Robotics

P +1 530-747-2735

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[glenn_varnon]

Tomas,

Have you determined the maximum solder void that the pins can see and still be functional?

Glenn Varnon

MFG Engineer | TechnipFMC Schilling Robotics

P +1 530-747-2735

glenn.varnon@technipfmc.com<mailto:glenn.varnon@technipfmc.com>

This email has been sent by or on behalf of TechnipFMC plc, a company registered in England and Wales with registered no. 09909709, and with its registered office address at One St. Paul’s Churchyard, London, EC4M 8AP, or one of its subsidiaries.