Frame Rx interrupt generation in independent mode is controlled by
RxQD[RxFIntM] - See Section 5.12.15.5.2 of LS1043ADPAARM. The interrupt
request is reflected in FMFP_FCEV and by default is masked in FMFP_CEE.
These registers are described in Sections 5.7.3.7 and 5.7.3.8, bit mapping
is defined in Section 5.12.22.
Further handling is done according to the global SoC mappings and
rules, refer to LS1043ARM, Chapter 5 and ARM GIC-400 Technical Reference Manual.
Have a great day,
Platon
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!
- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------