本文说明S32G  RDB2板Linux板级开发包BSP32 的ATF细节，以帮助客户了解S32G的ATF是如何运行的，以及如何修改到客户的新板上。   从BSP32开始，默认启动需要ATF支持，所以部分定制需要移动到ATF中，Uboot会简单很多。 请注意本文为培训和辅助文档，本文不是官方文档的替代，请一切以官方文档为准。   目录如下： 目录 1    S32G Linux文档说明... 2 2    创建S32G RDB2 Linux板级开发包编译环境... 3 2.1  创建yocto编译环境: 3 2.2  独立编译... 8 3    NXP ATF 原理... 13 3.1  AArch64 Exception Leve: 13 3.2  ATF原理... 14 3.3  ATF目录 结构... 16 3.4  ATF初始化流程... 25 3.5  NXP ATF的SCMI支持... 28 3.6  NXP ATF的PSCI支持... 32 3.7  NXP ATF OPTEE接口（未来增加）... 36 4    ATF 定制... 36 4.1  修改 DDR配置... 36 4.2  修改调试串口与IOMUX定制说明... 39 4.3  启动eMMC定制说明... 48 4.4  I2C与PMIC定制说明... 58

This doc explain our Linux BSP driver and how to custom them. Contests as follows: include bsp30/32 目录 1 S32G Linux文档说明 ................................................. 2 2 创建S32G RDB2 Linux板级开发包编译环境 .............. 2 2.1 创建yocto编译环境: ................................................ 2 2.2 独立编译 ................................................................. 8 3 Device Tree ............................................................. 11 3.1 恩智浦的device Tree结构 ..................................... 11 3.2 device Tree的由来(no updates) ............................ 13 3.3 device Tree的基础与语法(no updates) ................. 15 3.4 device Tree的代码分析(no updates) .................... 37 4 恩智浦S32G BSP 包文件目录结构 .......................... 70 5 恩智浦Linux BSP的编译(no updates) ...................... 72 5.1 需要编译哪些文件 ................................................ 72 5.2 如何编译这些文件 ................................................ 73 5.3 如何链接为目标文件及链接顺序 ........................... 74 5.4 kernel Kconfig ...................................................... 76 6 恩智浦BSP的内核初始化过程(no updates) .............. 76 6.1 初始化的汇编代码 ................................................ 78 6.2 初始化的C代码 ..................................................... 82 6.3 init_machine ......................................................... 94 7 恩智浦BSP的内核定制 ............................................. 97 7.1 DDR修改 .............................................................. 98 7.2 IO管脚配置与Pinctrl驱动 .................................... 100 7.3 新板bringup ........................................................ 121 7.4 更改调试串口 ...................................................... 125 7.5 uSDHC设备定制(eMMC flash,SDcard, SDIOcard) 129 7.6 GPIO驱动 ........................................................... 137 7.7 GPIO_Key 驱动定制 .......................................... 145 7.8 GPIO_LED 驱动定制 ......................................... 150 7.9 芯片内thermal驱动 ............................................. 155 7.10 CAN接口驱动 ..................................................... 157 7.11 I2C及外设驱动 .................................................... 162 7.12 SPI与SPI Slave驱动 ........................................... 183 7.13 Watchdog test. ................................................... 190 7.14 汽车级以太网驱动定制 (未验证) (未完成) ........... 191

Demo The driver does not use a steering wheel or pedals to control a car on a race. All he uses is the movement of his head to turn the car and his mouth to accelerate and stop.       Featured NXP Products   K64_120 |Kinetis K64 120 MHz MCUs|NXP Freedom Development Platform for Kinetis|NXP Sensor Fusion|NXP   Links Arrow SAM Project   Videos          

Demo Needs for insuring availability of Electrical Power is increasing. Batteries are spreading into automotive, electrical storage systems. This demo will demonstrate the Battery Management Product Family from NXP.   Most scalable and comprehensive battery management solutions Automotive robustness and in-house manufacturing process Designed for Functional Safety   Featured NXP Product 14-Channel Li-ion Battery Cell Controller IC|NXP   Target Applications Automotive Battery Chargers and Management 48V battery applications High-voltage battery management systems (> 800 V) Industrial Energy Storage Systems Uninterrupted power supply (UPS) E-bikes, E-scooters   Block Diagram

Demo Owner David Lopez This demo is an overview of our power management simulation and validation tools. Our tools will help you accelerate power management validation with ISO 26262 compliance. Through this demo you will discover how NXP develop innovative validation tool to cover multiple use case, and accelerate product validation in line with ISO26262. The leading device use to develop this tool is MC33908, System Basic Chip with DC/DC and highest functional safety level.  In addition this tool is also covering the validation of MCU and SBC attachment.  This tool contain a database made through the collection of different car OEM "non-ISO" pulse with fast execution.   Features Transient simulation tool platform Accelerate power management validation with ISO 26262 compliance Global OEM use cases database Featured NXP Products Analog and Power Management|NXP

Demo This solution showcases the i.MX 6QuadPlus along with the MMPF0100 Power Management to enable the 2D/3D cluster, infotainment and rear view camera.      Features: High performance smooth 3D graphics based on the i.MX 6QuadPlus applications processor running on Linux. On the fly rendering of the infotainment menu. Seamlessly integrate extremely responsive instruments and highly complex 3D content Optimal usage of the CPU and GPU to achieve high-end graphics on the power effective and system cost effective i.MX Switch between HD video playback and the rear view camera on the secondary display Menu can be blended over the map (BG layer) using transparency   _______________________________________________________________________________________________________________________ Featured NXP Products: Product Link i.MX 6QuadPlus Processor i.MX 6QuadPlus Applications Processors | Quad Arm® Cortex®-A9 with extreme graphics performance and enhanced power manag…  i.MX 6DualPlus Processor i.MX 6DualPlus Applications Processors | Dual Arm Cortex-A9 for extreme graphics performance| 1.2 GHz | NXP  14-Channel Configurable Power Management IC 14-Channel Configurable Power Management IC | NXP  SABRE for Automotive Infotainment Based on the i.MX 6 Series SABRE|Automotive-Infotainment|i.MX6 | NXP    _________________________________________________________________________________________________________________________   Screen shot 1: Cluster with 3D maps Real-Time 3D map (created in Blender): 640 abstract buildings. 20 different building types. 3 “special” buildings. One building type. 5x5 map grid. Dynamic, directional lighting. Calculating and updating car chase camera every frame. Smooth 3D animations even at 30 Hz. This is no video!     Screen shot 2: Secondary Display playing Video or RearView Camera

本文探讨了如何解决i.MX8MP EMC测试遇到的问题，主要针对辐射超标问题。除了硬件方案，着重探讨了LVDS展频等软件方案。

This application note explain how to run M kernel PFE master and A kernel PFE slave demo without bootloader support. chinese version: 在真实的产品中，一般会使用一个基于M7_0核的bootloader来启动M和A核，这个bootloader负责所有M核和A核资源的初始化，解决M核和A核的资源冲突，并且启动M和A核。所以理论上运行M PFE Master Mcal驱动加A PFE Slave Linux驱动也是需要一个bootloader的。参考文档《S32G_Bootloader_V*》，Johnli，可以在公开community上搜索获得。 本文讨论一种简易的办法，就是： S32G3 RDB3板子配置为SDcard启动，插入SDcard，里面放有PFE SLAVE驱动的Linux镜像。 上电启动后运行PFE Master工程的lauterbach调试脚本：run_main_G3_REV1_1.cmm，这个脚本会重启整个S32G3。 然后在脚本中用wait 10S的操作，这个时候Linux已经启动，并且使用Uboot的代码调用ATF来完成PFE相关pre-init, partition reset和时钟与管脚初始化(如上分析， EMAC0~2的RGMII IOMUX已经配置好)，然后Slave驱动会等待一段时间，等MCAL Master驱动加载，继续运行PFE Master MCAL代码后，Linux端Slave驱动也加载正确。然后就可以测试整个M Master/A Slave Demo。 总结：以上办法实际上是把bootloader应该做的PFE相关硬件初始化工作由Linux来完成，以便快速搭建Demo，这样客户在做真实的产品开发时，可以做为一个NXP release的标准参考。

This doc explain how to build a PFE master project on M7 and how to integration. chinese version. 目录 1 需要的软件与工具 ...................................................... 2 2 Master Demo编译说明 ............................................... 2 2.1 安装RTD_MCAL驱动 ............................................. 2 2.2 安装PFE_MCAL驱动 .............................................. 3 2.3 编译PFE master工程 .............................................. 3 3 修改为支持RDB板的RGMII接口 ................................ 4 3.1 硬件连接 ................................................................. 4 3.2 软件修改 ................................................................. 5 4 Master Demo测试 ...................................................... 7 4.1 硬件连接 ................................................................. 7 4.2 PFE_EMAC1(RGMII)测试过程 ............................... 7 5 Master Demo代码说明 ............................................... 8 6 集成中注意点 ........................................................... 11 6.1 PFE_PreInit .......................................................... 11 6.2 S32G3中的GENCTRL1的配置 ............................. 12 6.3 RX CLOCK重新锁定 ............................................ 13 7 Demo Debug建议 .................................................... 14 7.1 PFE相关寄存器说明 ............................................. 14   Contents 1 Required software and tools ...................................... 2 2 Master Demo compiling ............................................. 2 2.1 Install RTD_MCAL driver........................................ 2 2.2 Install PFE_MCAL driver ........................................ 3 2.3 Compile PFE master project .................................. 3 3 Change the demo to support RDB3 board RGMII port4 3.1 Hardware design .................................................... 4 3.2 Software modification ............................................. 5 4 Master DemoTest ...................................................... 7 4.1 Hardware design .................................................... 7 4.2 PFE_EMAC1(RGMII) test steps ............................. 7 5 Master Demo code flow ............................................. 8 6 Notes in integration .................................................. 11 6.1 PFE_PreInit .......................................................... 11 6.2 The GENCTRL1 configruation of S32G3 ............. 12 6.3 RX CLOCK relock ................................................ 13 7 Demo Debug suggestion ......................................... 14 7.1 PFE related registers ........................................... 14

结合MPC5748G的Lifecycle机制，阐述如何使用Lifecycle机制来满足在开发阶段及最终消费阶段对各利益相关方的数据进行保护的需求，比如Tier1的IP(知识产权)、OEM的一些标定参数、车主的个人隐私等。并介绍Lifecycle在每个阶段所支持的主要安全特性及如何配置使用。

This article explains the details and customization of the S32G M7 core Standby demo. And how to porting to Autosar Mcal demo. Contents 1    Description of reference materials. 2 2    Demo creation and running process. 2 2.1  Demo checkpoints. 2 2.2  The difference between Standby and StandbyRAMboot 4 3    S32G Standby principle and Code Description. 5 3.1  Peripheral initialization function. 5 3.2  standbyramc_cpy(optional) 5 3.3  WKPU_set 8 3.4  standby_modechange. 13 4    VR5510 PMIC Standby principle and code description. 15 4.1  PMIC_initConfig. 15 4.2  PMIC_standbyEntry. 17 5    Customization modification. 18 5.1  Do not enable RTC wakeup feaure. 18 5.2  Eable CAN1_RX wakeup feature. 19 5.3  Only support full boot 21 5.4  Open the DDR related power 21 5.5  Modify debug serial port to UART1. 24 5.6  Modify the device drive clock. 26 5.7  close other non-main core. 30 6    Build a new MCAL demo. 34 6.1  Modify the UART driver 35 6.2  Implement the clock shutdown code. 36 6.3  Configure the power mode switching driver 37 6.4  Confgure the wakeup source. 42 6.5  Add PMIC driver 51 6.6  Main function call routine. 59 6.7  Test 61 6.8  Future development plan. 62 本文说明S32G M7核Standby demo 详细情况及定制,以及如何新建一个mcal demo 录 1    参考资料说明... 2 2    Demo创建运行过程... 2 2.1  创建运行... 2 2.2  Standby和StandbyRAMboot的区别... 4 3    S32G Standby原理与代码说明... 5 3.1  外设初始化函数... 5 3.2  standbyramc_cpy(可选) 5 3.3  WKPU_set 8 3.4  standby_modechange. 13 4    VR5510 PMIC Standby原理与代码说明... 14 4.1  PMIC_initConfig. 14 4.2  PMIC_standbyEntry. 16 5    定制修改... 17 5.1  关闭RTC唤醒功能... 17 5.2  打开CAN1_RX唤醒功能... 19 5.3  只支持full boot 20 5.4  打开DDR相关电源... 21 5.5  修改调试串口为UART1. 23 5.6  修改设备驱动时钟... 25 5.7  事先关掉所有其它的非主核... 29 6    修改为MCAL Demo. 33 6.1  修改UART驱动... 34 6.2  实现时钟关闭代码... 35 6.3  配置电源模式切换驱动... 36 6.4  配置唤醒源... 41 6.5  加入PMIC驱动... 50 6.6  主函数逻辑实现... 58 6.7  运行测试... 60 6.8  未来开发计划... 61   attachment include chinese/english doc, s32ds codes with 2 zip package(remove the .7z), mcal codes.  

This doc explain how to modify the bootloader to boot linux&mcal, to solve the conflict between bootloader, mcal and linux   本文说明在S32G2 RDB2板上如何定制开发Bootloader，本文示例主要实现功能是： Bootloader启动一个M核，MCAL驱动测试程序，本文分别测试了MCU，DIO，UART的MCAL驱动示例代码。 Bootloader同时启动A53 Linux 目录 1    需要的软件，工具，文档与说明... 3 1.1  软件与工具... 3 1.2  参考文档... 3 1.3  开发说明... 3 2    测试软件安装编译说明... 4 2.1  安装RTD_MCAL驱动... 4 2.2  编译MCAL驱动测试程序(以MCU为例) 5 2.3  优化重排M7 demo镜像及与MPU设置的配合... 5 2.4  去掉CLOCK INIT. 7 2.5  去掉MCU相关INIT. 8 2.6  DIO MCAL程序去掉PORT INIT. 9 2.7  UART MCAL程序去掉PORT INIT. 10 2.8  UART MCAL程序修改CLOCK TREE.. 10 2.9  解决中断冲突... 11 2.10 准备A53 Linux镜像... 12 3    Bootloader工程说明... 13 3.1  关掉XRDC支持... 13 3.2  关掉eMMC/SD支持(可选) 14 3.3  关掉secure boot(可选) 14 3.4  增加MCAL驱动所需要的PORT的初始化... 15 3.5  解决Bootloader,MCAL与Linux的clock冲突... 17 3.6  配置A53 Boot sources: 34 3.7  配置M7 Boot sources: 35 3.8  关闭调试软断点：... 36 3.9  编译Bootloader工程... 37 3.10 制造Bootloader的带IVT的镜像... 38 3.11 烧写镜像... 41 4    测试... 42 4.1  硬件连接... 42 4.2  MCU MCAL+Linux测试过程... 42 4.3  DIO MCAL+Linux测试过程... 43 4.4  UART MCAL+Linux测试过程... 43 5    Bootloader源代码说明... 43 6    Bootloader定制说明... 45 6.1  QSPI NOR驱动说明... 45 6.2  eMMC/SDcard启动支持... 46 6.3  DDR初始化... 46 6.4  Secure Boot支持... 46 7    调试说明... 46 7.1  Bootloader的调试... 46 7.2  MCAL驱动的调试... 46   add one more doc to explain how to modify atf to boot on G3.

This doc explain how to support a new QSPI nor for boot, SDK and Linux, Contents as follows: 目录 1 硬件设计 .................................................................... 2 2 所需工具和相关资料 .................................................. 5 3 ROM Code的启动流程 ............................................... 5 4 S32G QSPI NOR flash配置表头定制 ......................... 7 4.1 S32G QSPI NOR启动配置表信息 .......................... 7 4.2 目前支持的配置表头分析说明 ............................... 10 4.3 LUT构成与Flash write Data说明 ........................... 16 4.4 具体分析已有的配置表头的LUT与Flash write Data的 配置方法 ...................................................................... 22 4.5 支持一款新的QSPI NOR Flash示例1:Micron........ 28 4.6 支持一款新的QSPI NOR Flash示例2:Winbond .... 31 5 使用IVT打包配置头 .................................................. 33 6 使用IVT工具中的flash image工具烧写镜像到QSPI NOR 中 34 7 软件定制M7 ............................................................. 35 8 软件定制uboot ......................................................... 37 9 软件定制Linux Kernel .............................................. 40 9.1 支持美光8bit DDR 模式(未验证) .......................... 44 9.2 支持1bit SDR fast read 模式 ............................... 46 10 Debug过程中需要注意的几点 .................................. 49 10.1 启动时ROM Code读取QSPI NOR时钟仅有12Mhz左 右 49 10.2 比较大的镜像如果不加参数头，无法从QSPI-NOR上启 动 55   add a new doc for lauterbach driver: S32G How to Develop the QSPI-Nor Lauterbach Script 目录 1    背景和参考资料... 2 1.1  背景说明... 2 1.2  参考资料... 2 2    高速读开发流程... 3 2.1  时钟相关修改... 5 2.2  Lut配置说明... 6 2.3  QSPI NOR控制器配置... 12 2.4  QuadSPI_Write32BytesDOPI读函数分析... 15 2.5  增加AHB read寄存器配置... 17 2.6  测试结果... 18 3    高速写开发流程... 19 3.1  Erase lut分析及调用... 19 3.2  Write lut分析及调用... 21 3.3  测试结果... 22 3.4  Lauterbach烧写镜像脚本说明... 22

目录 1 S32G Linux文档说明 .................................................. 3 2 创建S32G RDB2 Linux板级开发包编译环境 .............. 4 2.1 创建yocto编译环境: ................................................. 4 2.2 独立编译 ................................................................. 9 3 FSL Uboot 定制 ........................................................ 14 3.1 FDT支持 ............................................................... 14 3.2 DM(driver model)支持 ........................................... 20 3.3 Uboot目录结构 ...................................................... 31 3.4 Uboot编译 ............................................................. 34 3.5 Uboot初始化流程 .................................................. 35 3.6 使能了ATF后对Uboot初始化流程的影响 ............... 40 4 Uboot 定制 ............................................................... 41 4.1 修改 DDR大小 ....................................................... 41 4.2 修改调试串口与IOMUX说明 .................................. 44 4.3 DM I2C与PMIC初始化 .......................................... 53 4.4 通用GPIO ............................................................. 59 4.5 启动eMMC定制 ..................................................... 69 4.6 Ethernet定制 ......................................................... 78 5 Uboot debug信息 ..................................................... 89 5.1 Print env ............................................................... 89 5.2 dm - Driver model low level access ...................... 92 5.3 fdt .......................................................................... 95 5.4 I2C测试 ................................................................. 95 5.5 芯片寄存器访问 ..................................................... 98 updated to V5

This doc explain our Mcal driver and how to custome them. contents as follows: 目录 1 AutoSAR MCAL基本概念 .......................................... 2 1.1 AutoSAR目标 ......................................................... 2 1.2 AutoSAR概念 ......................................................... 2 1.3 AutoSAR基本方法 .................................................. 2 1.4 BSW(Basic Software) ............................................. 4 1.5 NXP Basic AutoSAR软件 ....................................... 4 1.6 RTE与BSW的配置 ................................................. 5 1.7 BSW的配置流程 ..................................................... 6 1.8 MCAL驱动 .............................................................. 7 2 MCAL工具 ................................................................. 7 3 MCAL说明 ................................................................. 8 3.1 MCAL的下载与说明 ................................................ 8 3.2 EB Tresos的下载，安装 ....................................... 13 3.3 RTD-MCAL安装 ................................................... 16 3.4 Trace32的下载与安装 .......................................... 18 3.5 样例工程的编译，运行 ......................................... 20 4 MCAL驱动配置与定制 ............................................. 40 4.1 MCU ..................................................................... 45 4.2 PORT ................................................................... 59 4.3 DIO ....................................................................... 69 4.4 FlexCAN ............................................................... 71 4.5 FlexLin ................................................................. 87 4.6 GMAC .................................................................. 93 4.7 I2C ..................................................................... 101 4.8 PMIC .................................................................. 108 4.9 PMIC WDOG ...................................................... 127 4.10 WDOG ............................................................... 137 4.11 UART ................................................................. 144 4.12 SPI ..................................................................... 149 4.13 PWM .................................................................. 165 4.14 ADC ................................................................... 171 4.15 Thermal .............................................................. 177

This doc explain how to configure a new LPDDR4 and test it on S32G, contents as follows: 目录 1    硬件资源，文档及工具下载... 2 1.1    硬件资源... 2 1.2    内存配置测试相关的文档... 2 1.3    内存配置与压力测试工具. 3 2    内存设计要求... 3 3    LPDDR4基础... 3 3.1    基本知识... 3 3.2    Inline ECC.. 4 4    硬件连接... 6 5    S32G+LPDDR4内存配置与测试步骤... 8 5.1    配置LPDDR4初始化寄存器设置... 9 5.2    使用内存测试工具初始化PHY及生成DDRC配置Uboot源代码    11 5.3    生成DDRC配置ATF源代码(从BSP32开始) 14 5.4    测试内存... 18 5.5    其它尺寸的LPDDR4配置... 19 6    测试失败的DEBUG.. 24 7    内存参数应用到Uboot中... 25 8    内存参数应用到ATF中... 25 9    附录... 25 9.1    一个重要的DDR TOOL bug Fix. 25 9.2    Uboot DDR测试工具... 26 9.3    Kernel DDR测试工具... 27 9.4    附DDR tool测试项截图... 28   Contents 1    Hardware Materials, Docs and Tools Needed. 2 1.1    Hardware resource. 2 1.2    Related docs of memory configuration and test 2 1.3    Memory configuration and test tools. 3 2    Memory Hardware Design Requirement 3 3    LPDDR4 Basics. 3 3.1    Basic Knowledge. 3 3.2    Inline ECC.. 5 4    Hardware Design. 7 5    S32G+LPDDR4 Memory Configuration and Test Steps. 8 5.1    Configure LPDDR4 DDRC Register Settings. 9 5.2    Use the Memory Test Tool to Initialize the PHY and Generate the DDRC Configuration Uboot Source Code  12 5.3    Generate ddrc configuration ATF source code (starting from bsp32) 15 5.4    Memory Test 19 5.5    Other size LPDDR4 configurations. 20 6    Debug of the Fails of Test 25 7    Modify the DDRC register settings in Uboot 26 8    Modify the DDRC register settings in ATF. 26 9    Appendix. 26 9.1    A importance DDR TOOL bug Fix. 26 9.2    Uboot DDR Test Tools. 27 9.3    Kernel DDR Test Tool 28 9.4    Attached Screenshot of DDR Tool Test Items. 29

This doc explain  where is the design resource and what they are of S32G in Chinese,  Contents as follows: 目录 1 www.nxp.com 官网资源 ............................................. 2 1.1 www.nxp.com Documentation ................................ 4 1.2 www.nxp.com Tools&Software ............................. 10 2 Flexera资源 ............................................................. 18 2.1 Automotive HW-S32G Evaluation Board .............. 21 2.2 Automotive HW-S32G GoldBox ........................... 22 2.3 Automotive HW-S32G RDB2(RDB不再说明) ....... 22 2.4 Automotive SW-S32G2 Standard Software.......... 23 2.5 Automotive SW-S32G2 reference Software ......... 28 2.6 Automotive SW-S32G2 Tools .............................. 30 3 Docstore资源 ........................................................... 31

Introduction Background There is not an official data for PCIe latency and performance, while some customers pay attention to and request these data. This paper utilizes Lmbench lat_mem_rd tool and DPDK qdma_demo to test the PCIe latency and performance separately. Requirement 1) Plug Advantech iNIC (LX2160A) into LX2160ARDB. 2) Configure EP ATU outbound window at console. 3) Apply the patch to lmbench-3.0-a9, and recompile lmbench tool. 4) There is qdma_demo in iNIC kernel rootfs by default. Test Environment     PCIe Latency Overview   Direction Description Latency(ns) PCIe(Gen3 x8) – DDR read from EP to RC 900 PCIe – PCIe – DDR Read from EP to EP (through CCN-508) 1550 PCIe – PCIe – DDR Read from EP to EP (through HSIO NOC) 1500 Setup 1) LX2160ARDB 2) iNIC – PCIe EP Gen3 x8 with LX2160A 3) Test App running at iNIC: Lmbench lat_mem_rd   # ./lat_mem_rd_pcie -P 1 -t 1m   PCIe Performance Overview    Direction Throughput (Gbps) PCIe EP to EP 50   Setup 1) LX2160ARDB 2) iNIC – PCIe EP Gen3 x8 with LX2160A 3) Test App : qdma_demo running at iNIC   $./qdma_demo -c 0x8001 -- --pci_addr=0x924fa00000 --packet_size=1024 --test_case=mem_to_pci Peer to Peer On LX2 Rev. 2      Products   Product Category NXP Part Number URL MPU LX2160A https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-lx2160a-lx2120a-lx2080a-processors:LX2160A LSDK software Layerscape Software Development Kit https://www.nxp.com/design/software/embedded-software/linux-software-and-development-tools/layerscape-software-development-kit:LAYERSCAPE-SDK   Tools    NXP Development Board URL LX2160ARDB https://www.nxp.com/design/qoriq-developer-resources/layerscape-lx2160a-reference-design-board:LX2160A-RDB Advantech ESP2120 Card      

        S32G just support serial download a M7 image to run by internal rom codes, our S32G DS IDE have a flash tools to use this feature to burn the image to external device. So current image burn method will divide into 2 step: 1: burn a uboot into the external device by S32G DS flash tools. 2: reboot the codes with uboot and run with network to burn the linux image into external device.      which need two working place on manufacture line, and customer wish to have a one time on-line tools, which means we need use serial port to boot uboot directly but S32G rom codes do not support it.       We have a reference tools of S32V but which IP difference is big between on S32V and S32G, So we can not reuse it and have to develop a new one.       The development working include: 序号 开发工作 说明 开发者 1 开发 根据S32G的serial boot协议要求，开发PC端的串口工具来下载M7镜像 John.Li 2 开发 根据自定义协议要求，开发PC端的串口工具来下载A核Bootloader到SRAM中 John.Li 3 开发 根据自定义协议要求，开发M7镜像的串口接收与Checksum逻辑 John.Li 4 开发 修改M7镜像支持串口0 John.Li 5 开发 开发实现M7镜像的串口单字节同步收发函数 John.Li 6 开发 开发实现A53启动功能 John.Li 7 调试与Debug 调试解决串口接收乱码问题(Serial boot rom codes仍然在回送消息串口) John.Li 8 调试与Debug 提供 解决A核启动串口halt思路(Serial boot rom codes仍然占用串口) John.Li 9 调试与Debug 优化M7镜像，缩小大小 Tony.Zhang 10 调试与Debug 根据M7镜像和A核 Uboot在SRAM中的内存分配要求，重排M7镜像位置，避免冲突 Tony.Zhang 11 调试与Debug 在M7中初始化SRAM空间 Tony.Zhang 12 调试与Debug 在M7中设置SRAM可执行空间 Tony.Zhang 13 调试与Debug 调试解决由于cache没有及时回写导致的下载镜像错误的问题 Tony.Zhang 14 调试与Debug 集成，调优与文档 John.Li   Pls check the attachment for the doc/codes/binary release which include:    Release      |->M7: Linflexd_Uart_Ip_Example_S32G274A_M7: S32DS M7工程。      |->PC: s32gSerialBoot_Csharp: PC端的Visual Studio的C#的串口工具工程。      |->Test:      |    |-> 115200_bootloader.bin: S32DS M7工程编译出来的bin文件，波特率为115200      |    |-> 921600_bootloader.bin: S32DS M7工程编译出来的bin文件，波特率为921600      |    |->load_uboot.bat: 运行工具的批处理文件，运行成功后打开串口可以看到Uboot执行，默认使用的波特率是115299         |    |->readme.txt:其它测试命令 |    |->s32gSerialBoot.exe:编译出来的PC端串口工具 |    |->u-boot.bin: BSP29默认编译出来的u-boot.bin.      Product Category NXP Part Number URL Auto MPU     S32G274     https://www.nxp.com/s32g    

Overview The S12ZVH-REF-V1 is a reference design engineered for being a design base for starting an instrument cluster project, also it helps to reducing Automotive Cluster development time and maximizing engineering resources. Based on the 16-bit S12 MagniV® S12ZVH mixed-signal microcontrollers, the S12ZVH-REF-V1 provides a production-looking design with impressive integration. The S12ZVH-REF-V1 reference design is not only provided as a hardware reference but also as a software and mechanical design. Block Diagram   Products Product Features S12ZVH MagniV Mixed-signal MCU  16-bit S12 MagniV® S12ZVH mixed-signal microcontrollers for instrument cluster.   Features Interfaces   LIN physical transceiver and connector CAN connector interfaced with MCUs CAN physical transceiver Components 1 x custom 160 segment LCD 1 x low-power piezoelectric speaker 4 x stepper motors 49 x LEDs used as telltales and backlights 6 x user buttons 2 x potentiometers S12ZVH The S12ZVH-REF-V1 does not include on-board programming/debugging circuitry; it requires an external programmer compatible with the BDM protocol. Files S12ZVH-REF-V1 Mechanical and Assembly files  S12ZVH-REF-V1 Reference Design Software (CW10.5)