NXP’s new 65 V LDMOS technology: designed for ease of use

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NXP’s new 65 V LDMOS technology: designed for ease of use

NXP’s new 65 V LDMOS technology: designed for ease of use

Demo

Benefits

1. More power – Higher voltage enables higher power density, which helps reduce the number of transistors to combine.
2. Faster development time – With higher voltage, the output power can be increased while retaining a reasonable output impedance.
3. Design Reuse – This impedance benefit also ensures pin-compatibility with current 50 V LDMOS transistors for better scalability.
4. Manageable current level – Higher voltage reduces the current losses in the system.
5. Wide safety margin – The higher breakdown voltage of 182 V improves ruggedness and allows for higher efficiency classes of operation

Products

Training

65 V LDMOS Introduction

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Other Links

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Version history
Last update:
‎05-30-2017 02:14 PM
Updated by:
NXP Employee