Why is connecting 100 nF external capacitors in parallel to a GPIO pad advised for NHS3152 over NFC?

[acuom]

I was reading the NHS3152 data sheet and came across this advise:

"When on NFC power only (passive operation), connecting one or more 100 nF external capacitors in parallel to a GPIO pad and setting that pad as an output driven to logic 1, is advised. A high-drive pin must be chosen and several pins can be connected in parallel."

It sounds like useful advice so I was just wondering what's the rationale behind it? I am currently trying to power my NHS3152 demo board over NFC (1.8V between GND and GPIO) to read a photodetector (~1.2kOhms dark resistance) using the DAC-ADC-I2D setup and the board keeps restarting even though the DAC is only applying a voltage of 1.2V.

It, however, doesn't restart if I use the GPIO pin to drive the detector instead of the DAC and I am able to read values on the I2D, but I am not sure if that's safe to do in the long run. So I was thinking I can avoid doing the latter if I am able to overcome the issue with the DAC-ADC-I2D setup and this advice (in the data sheet) seemed like it might be related.

[driesmoors]

Hi,

The external capacitors help in reducing the voltage drop when performing taxing operations. Writing to NVM comes directly to mind, but generally everything you do will add to the load, and in a passive setup, you only start with 1.85V.
It definitely is useful advice :-), but needs corresponding firmware that ensures the capacitors are charged slowly prior to performing a short, taxing operation.

To know how much leniency you have left (I'm guessing: almost nothing), set an unused PIO high in output mode and measure the Voltage using a probe, then watch it drop when the operations are started.

In your setup, I would suggest (if not done already):

• Lower your SysClock to the maximum possible
• Disable EEPROM before starting your ADC/DAC/I2D operations.
• Your photodetector will draw quite some current, about 1 mA. If possible (since it will diminish the difference between light/dark), add a resistor in series.

Keep in mind that some operations require a minimum SysClock. See the firmware documentation in the SDK (firmware.html > SW Clock Restrictions).

KR,
Dries.

[acuom]

Hi @driesmoors,

Thank you for the detailed explanation. Just to ensure I am connecting the right pins, which of the 12 pins are the high current GPIO? I remember reading in the data sheet it was 4 of them but I don't remember seeing the exact numbers.

I shall also try the other suggestions later today. I had tried attaching a resistor in series however that made it impossible to distinguish between dark and light (our sensor is custom made and quite noisy, It draws a current of just 0.16mA though).

Essentially, the DAC-Sensor-I2D/ADC setup works (as in the board doesn't restart but output remains noisy) if I use a lower voltage value of 1500. Is it safe to replace the DAC with the GPIO pin to drive the sensor since that seemed to be preventing board restarts too?

[driesmoors]

Hi,

From the NHS3152 datasheet (Functional description > PIO0 current source mode)

PIO0_3, PIO0_7, PIO0_10 and PIO0_11 are high-source pads that can deliver up to
20 mA to the load.

Pins 10 and 11 are needed for a debug connection. Be careful not to lock yourself out!

Is it safe to replace the DAC with the GPIO pin to drive the sensor

Yes. But you will have to measure the voltage being output, of course.

KR,
Dries.

[acuom]

Hi,

Thank you for pointing me in the right direction!

I tried switching the EEPROM off while DAC operations were underway and that prevented the board from restarting!

However, we are continuously interrogating this photodetector (essentially a while loop runs until the shared memory buffer is full, the data is then written to EEPROM, acquired by an android app and the process repeats until NFC is taken away). If I constantly switch the EEPROM on and off in this loop, wouldn't I hit the 10,000 cycles limit much quicker since I now have two sets of flushes occurring (during DeInit and during my write operations (486 bytes of data is written each time)?

Would you recommend an alternative way of reducing EEPROM wear or powering down using peripheral access functions like Chip_Syscon_Peripheral_DisablePower? Instead of writing all the bytes, I could only write bytes that have changed for instance?

[driesmoors · Accepted solution]

Hi,

Some thoughts:

• The write endurance limit is per eeprom page (64 bytes). It is a minimum guaranteed write count. If your ambient temperature is closer to room or fridge temperatures, or lower, I expect this to be much higher, but I have no way to quantize this.
• Do you need data retention? From the description, I understand the NFC reader has already retrieved the data before the NFC field is removed, abruptly shutting down the IC. If not needed, you can store the data in SRAM, or directly in the NFC shared memory.
• Mind that data corruption can occur when in a passive setup the NFC field is removed while flushing EEPROM contents.
• 10.000 may not sound like much, but if a single person has to physically move his phone to the tag and read the data that number of times, it will still take quite some time before you hit that limit.

Kind regards,
Dries.

[acuom]

I think I had misunderstood the shared memory as being part of the EEPROM. Thank you for clarifying! Have been able to get it all to work now. 

Thank you once again for all your help with debugging this. Since I am only concerned with real time data and can make the assumption of the reader always being in range, I was able to turn off the use of EEPROM and stick to using the shared memory!

[fangfang]

Hello @acuom ,

Thanks for your information.

>> 100 nF external capacitors
The capacitor are decoupling capacitors. About the function of decoupling capacitors you can find more information on internet.

Have a nice day.

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[acuom]

Just following up on this in case someone can help!?