PN5180 AGC_REF_CONFIG not writable

[geoffreyvanland]

Hi,

I've been testing the PN5180 paired with ST MCU. Until now I succeeded in getting r/w registers to work, r/w eeprom to work, scan Vicinity cards and r/w block data. However I fail to get the LPCD mode to work, more specifically because writing to register AGC_REF_CONFIG (0x26) fails. If for example I want to use gear 15 I'd write 0x003C00 to the register. Reading that registers afterwards doesn't however reflect that change: the gear is not changed. I'm confided that the "write register" code is not problematic since I'm perfectly able to read/write the IRQ_ENABLE register.

What action should I need to take so that I'm able to set the AGC gear in register 0x26?

I've been using a custom implemented library derived from https://github.com/ATrappmann/PN5180-Library.

Here is are some debug traces:

[DBG ][PN5180]: Write Register 0x26, value=0x00003C66

[DBG ][PN5180]: Sending SPI frame: '
[DBG ][PN5180]: 00
[DBG ][PN5180]:
[DBG ][PN5180]: 26
[DBG ][PN5180]:
[DBG ][PN5180]: 66
[DBG ][PN5180]:
[DBG ][PN5180]: 3C
[DBG ][PN5180]:
[DBG ][PN5180]: 00
[DBG ][PN5180]:
[DBG ][PN5180]: 00
[DBG ][PN5180]: '

[DBG ][PN5180]: Reading register 0x26...

[DBG ][PN5180]: Sending SPI frame: '
[DBG ][PN5180]: 04
[DBG ][PN5180]:
[DBG ][PN5180]: 26
[DBG ][PN5180]: '

[DBG ][PN5180]: Receiving SPI frame...

[DBG ][PN5180]: Received:
[DBG ][PN5180]: 84
[DBG ][PN5180]:
[DBG ][PN5180]: 00
[DBG ][PN5180]:
[DBG ][PN5180]: 00
[DBG ][PN5180]:
[DBG ][PN5180]: 00
[DBG ][PN5180]: '

[DBG ][PN5180]: Register value=0x00000084

LPCD Reference Value [0x00000084]: AGC Gear=0, AGC Value=0084

[ahmedmomar88]

Hi,

I am using the NXP PNEV5180B V2.0 Evaluation Board with firmware version 4.0. I am also observing there is something wrong with the LPCD mode, a basic question is that I am not able to find the EEPROM address where the "AGC Reference" is stored?

The LPCD should succeed when the Current_AGC > AGC_Reference + AGC_Threshold

I am able to read "Current_AGC" and to read/write the "AGC_Threshold". Where to read/write "AGC_Reference"??

[Kan_Li]

Did you do DPC Calibration and set up to 15 gears in that device? Please kindly refer to https://www.nxp.com/docs/en/application-note/AN11742.pdf  and https://www.nxp.com/docs/en/application-note/AN11741.pdf  for details.

Hope that helps,

Have a great day,
Kan

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!
- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

[geoffreyvanland]

Additionally I would like to add that I'm testing using following shield.

The chip has following number: PN5180A. The FW version is 3.5. The EEPROM version is 00 91.

The NXP PNEV5180B V2.0 Evaluation Board has a chip with following number: PN518C3. The FW version is 4.0. The EEPROM version is 00 99.

[Kan_Li]

Thanks for the information! I will check with the expert and let you know when I have any feedback.

Thanks for your patience!

Have a great day,
Kan

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!
- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

[geoffreyvanland]

No, not at that time.

I've skimmed through both suggested Application Notes but there is no mention of how this is related to configuring LPCD.

As a test I've now tried with writing following EEPROM addresses:

0x59 - DPC_CONTROL to 0x53 (dpc=enabled, gear step size=1, start gear=5)

0x81 - DPC_AGC_GEAR_LUT_SIZE to 0x05

And afterwards write to register

0x26 - AGC_REF_CONFIG  value 0x00001466 (gear 5)

After reading that same register I once again get value 0x00000085, so it didn't take the GEAR.

With NFC Cockpit I can perfectly read AGC_REF_CONFIG, change gears and write. Next time I read AGC_REF_CONFIG it uses the applied gears. Or is this not suppose to happen?

I've also done some tests with NFC Cockpit (4.8 - latest), but I found a lot of issues with it...

Using LPCD EEConfig Self_Calibration I noticed it would write value 0x01 into registers 0x38 (LPCD Ref Value Selection). Still, the PN5180 datasheet clearly mentions that value 0x01 is autocalibration using RF_Checkcard function). Is this a bug in NFC Cockpit? Applying Auto_calibration via Update EEPROM Config would also write the wrong values into the 0x34 EEPROM address. For example selecting Gear 15 would program 0x34 as 0x0F and 0x35 as 0x00. Though the PN5180 datasheet mentions that 9:0 are AGC reference value where bit 13:10 are AGC gear.  (read below)

Using LPCD EEConfig Auto_Calibration I noticed it would write value 0x00 into registers 0x38 (LPCD Ref Value  Selection). Still, the PN5180 datasheet clearly mentions that value 0x00 selects the EEPROM reference value. Is this a bug in NFC Cockpit? And why doesn't it write the AGC Value into EEPROM, but only the gear?  (read below)

And what about LPCD Ref Value Selection 0x02? That seems to be missing in NFC Cockpit, though "Write AGCREF_CONFIG register" actually does exactly that (though only for the gears)! (read below)

[geoffreyvanland]

It seems there are quite some differences between older chips with older firmware, and newer chips which run the latest firmware.

For instance EEPROM address: LPCD_REFERENCE_VALUE (0x34)

• PN5180A0xx-C1-C2, fw 3.5:
  2 bytes: bit 9:0 AGC reference value; bit 13:10 AGC gear
• PN5180A0xx-C3, fw 4.0:
  2 bytes: bit 15:4 RFU; bit 3:0 AGC gear
  so NFC Cockpit was reading/writing that address correctly

And also EEPROM address LPCD_REFVAL_CONTROL aka LPCD_REFVAL_GPO_CONTROL (0x38)

•  PN5180A0xx-C1-C2, fw <= 3.5:
  LPCD_REFVAL_CONTROL
  1 byte: bit 1:0 Defines the source of the LPCD reference value
  00b Use EEPROM value for reference value
  01b Use one AGC measurement to get reference value
  10b Use AGC Reference value and AGC gear from the register AGC_REF_CONFIG. Though on page 50 it says: Use the Register value of CHECK_CARD_RESULT for reference value. This allows the configuration of the reference value without EEPROM programming.
  11b RFU
• PN5180A0xx-C1-C2, fw > 3.6:
  LPCD_REFVAL_GPO_CONTROL
  1 byte: bit 1:0 Defines the source of the LPCD reference value
  00b Use EEPROM value for reference value
  01b Use one AGC measurement to get reference value
  10b Use AGC Reference value and AGC gear from the register AGC_REF_CONFIG.
  11b RFU
• PN5180A0xx-C3, fw 3.A:
  LPCD_REFVAL_CONTROL
  1 byte: bit 1:0 Defines the source of the LPCD reference value
  00b Use EEPROM value for reference value
  01b Use one AGC measurement to get reference value
  10b Use AGC Reference value and AGC gear from the register AGC_REF_CONFIG.
  11b RFU
• PN5180A0xx-C3, fw 4.0:
  LPCD_REFVAL_GPO_CONTROL
  1 byte: bit 1:0 Defines the source of the LPCD reference value
  00b LPCD AUTO CALIBRATION
  01b LPCD SELF CALIBRATION
  10b RFU
  11b RFU
  this explains why NFC cockpit only shows these modes for the NXP PNEV5180B V2.0 Evaluation Board

For register CECK_CARD_RESULT aka AGC_REF_CONFIG (0x26):

   reading => perform a check card routine

   writing => uses the register value as LPCD reference when LPCD mode is 2.

   the behavior is the same across all datasheet / fw, though note that PN5180A0xx-C3, fw 4.0 doesn't support LPCD mode 2, it's RFU.

   doesn't explain why the write-read cycle that I'm trying to accomplish doesn't work on PN5180A0xx-C1-C2, fw 3.5, but does work on PN5180A0xx-C3, fw 4.0.

[Kan_Li]

There is something inconsistent with data sheet of PN5180A0XX-C3.