Hi,
I'm developing with the NTAG5 link, is there an errata document for this chip?
Because I've been noticing some strange when communicating in pass-though mode, i.e. when continuosly and simultaneous polling the SRAM_DATA_READY and/or NFC_IF_locked session registers from the I2C and NFC perspectives, sometimes the chip seems to enter in a blocked state where not even access to the session registers is possible...
What may be causing this?
Thank you.
I am also developing a pass-through mode with NTAG5 link and experiencing no communication for SRAM transfer. Here, the same procedure is used as described in AN12364 document. Also want to know about the ED pin clear session register correct address, because I found different addresses in datasheet and the AN12364 document.
Hello @tedarcpicker, Good Day!
Thank you very much for your interest in our products.
I would like to ask if you could you please describe the process that you have been following? And if you could please provide more details on your setup, such as what are the software libraries used to communicate via NFC? I would also like to ask what is the specific error that you are getting and when does it happen? Is it related to the NTAG not responding to the NFC/I2C commands?
Please consider that for proper communication using pass-through mode, some bits on the session registers need to be handled via I2C. You may find a detailed description of the pass-through mode communication process in the NTAG 5 - Bidirectional data exchange Application Note, along with the registers that have to be written.
You may find the name of those bits and their effects in section 8.1.4 and section 8.1.3.13 of the NTAG 5 Data Sheet.
My best regards,
Daniel.
Hello @tedarcpicker, Good Day!
Please refer to section 6.2 of the NTAG 5 - Bidirectional data exchange Application Note in which you will find a detailed description of the specific process that has to be followed when using pass-through mode to transfer data from an I2C host to the NFC reader device.
Please consider that in this mode the NFC device cannot read the SRAM constantly all the time since, it has to wait for the SRAM_DATA_READY (from the status register) bit to be set to 1 before sending the SRAM_READ command.
Consider as well that a specific configuration for this mode has to be set by the I2C host by writing to the session CONFIG_x_REG and ED_CONFIG_REG. For further details please refer to section 8.1.4 of the NTAG 5 link - NFC Forum-compliant I2C bridge.
After configuring these registers as described in the application note, the I2C host will write the SRAM blocks, and then wait for a LOW state on the ED pin, condition that will be met when the last byte of SRAM data has been read via NFC then, the host can access SRAM again.
An important aspect to highlight is that the ED pin is an active LOW signal. So due to open-drain implementation, you may consider adding an external pull-up resistor on this pin to ensure its logical state when inactive.
Additionally, I would like to ask if you are using a development kit for the NTAG 5 link such as the OM2NTP5332 Or is it a custom board?
My best regards,
Daniel.
Hello @tedarcpicker, Good Day!
Data rate in pass-through mode depends fully on the individually set data rates for each NTAG interface (I2C or NFC). Consider that the NTAG 5 I2C slave interface supports both standard (up to 100 kHz) and fast mode (up to 400 kHz) communication speeds for both read and write. Bitrates supported for NFC communication are described in Tables 112 and 113 of the NTAG 5 link Data Sheet.
Please consider that in pass-through mode, only one interface is active at a time for preventing timing issues, since they should be waiting for the SRAM to be accessible by checking SRAM_DATA_READY, PT_TRANSFER_DIR and the ED pin respectively. Please ensure the flow described in NTAG 5 - Bidirectional data exchange Application Note is being met at implementation.
My best regards,
Daniel.
Hello @tedarcpicker, Good Day!
Subcarrier mode is selected by the NFC reader using the first bit of the field "flags" in the protocol header. For further details please refer to section 7 of the International Standard ''ISO/IEC 15693-3''.
My best regards,
Daniel.
Hello @tedarcpicker, Good Day!
Please consider that NTAG5 pass-through mode is meant to be implemented for an efficient communication between an I2C host and an NFC reader device, enabling this mode would eliminate the need for any delays, since the flow is based on the polling of the flags SRAM_DATA_READY and PT_TRANSFER_DIR, so any additional delays could cause pass-through mode to not work as expected.
I would like to ask if you could please confirm that the SRAM is trying to be read by the NFC device, or are you trying to read the SRAM with the same I2C device with which it was written?
Please take into account that a reading from NFC device can only happen when SRAM_DATA_READY = 1, and this flag will be set to 1 after the I2C device is finished writing. Once the memory has been read by the NFC device, the flag will be set to 0 and it won't equal 1 again unless the SRAM is written again by the I2C host.
My best regards,
Daniel.
Hello @tedarcpicker, Good Day!
Please note that the I2C bus standard mode can transfer data at a rate of up to 100 kHz in standard mode and 400 kHz in fast mode, this does not imply that communication will not work with lower frequencies, however if the goal is to increment data rate for efficient communication, you may consider increasing the I2C bus frequency to a rate closer to the ones supported.
I would like to ask how many successful readings of the SRAM via NFC are taking place? Is it just the first one that is successful and all readings after that return "010F"?
I would also like to ask, after the NFC device reads the memory is the MCU writing to the SRAM again? Or does the MCU only write the memory once?
My best regards,
Daniel.
Hello @tedarcpicker, Good Day!
For a proper implementation of the pass-through mode please ensure the following configuration of the session registers is being handled correctly by the MCU before writing to the SRAM for the first time:
Consider that the ED pin has to be used in this mode since a logic LOW state on this pin will let the MCU know that it can write again to the SRAM. Additionally, note that any delays will interfere with the flow of the pass-through mode, I would strongly recommend to constantly read the configuration registers from the NFC side with the READ_CONFIG_REG command (A0h) to check SRAM_DATA_READY == 1.
Please consider that a 300Hz frequency on the I2C side would lead to a relatively slow communication speed.
To increase the data rate in this mode, please increase the I2C frequency to around 100kHz for standard mode.
My best regards,
Daniel.