Impedance control traces for CLRC663/MFRC630

[mhooper]

The schematics for CLEV6630B V2.0 development kit specify impedance control in the PCB specifications.  Is more information available about these specifications?

The impedance table specifies the impedance for the differential pair as 90 ohm.  Is this true across all implementations of the CLRC663 family?

Does this apply to just the TX traces?

Is the spacing relative to the TVSS trace?  Is there a specified trace width for the TVSS trace?

Over which sections of the traces must the width/spacing be controlled?  From the IC to the matching network?  Through the matching network?

The table makes reference to traces on layers 3 and 4 however the analog lines seem to exist solely on layer 1?

Thanks in advance for your assistance.

EDIT: This is in reference to the schematics for this kit: OM26630 | CLRC663 plus NFC Development Kit | NXP 

[IvanRuiz]

Hello,

That is the specification under which the evaluation board was made. You may also consider the Layout recommendations for the a more critical par such as the antenna design, please refer to chapter 3.2 of following App Note: https://www.nxp.com/docs/en/application-note/AN11019.pdf 

Hope it helps!

BR,

Ivan.