IRQ register of PN5180

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IRQ register of PN5180

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smiwa
Contributor III

Hi Christian san,

Though maybe something minor, could you tell me the relation of register of IRQ_ENABLE register, IRQ STATUS register, and IRQ_SET_CLEAR register?

For bit 0 to 13, all bits are corresponded respectively. But for bit 14 to 20, those bits are not corresponded.

In Library, it sometimes reads status register and stores it in some buffer such as "dwIrqWaitFor". And it uses its buffer to IRQ_ENABLE/DISABLE setting by ~dwIrqWaitFor. In this case, I think all bits should be corresponding among 3 registers each other. Or bit14 to 20 are not needed to use to control PN5180?

Thank you for your supports!

Best regards,

   s. Miwa 

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Kan_Li
NXP TechSupport
NXP TechSupport

Hi S.Miwa,

Are you referring to the following code snippet? Please kindly help to clarify. Thanks for your patience!

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Have a great day,
Kan

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