I2C specification of NT3H2111

[masafumishimura]

Hello NXP Semiconductor engineers

My customer asked us following I2C specification of NR3H2111.

Would you please confirm?

(1)

Could you show me whether NT3H2111 supports I2C software reset (Start-Cond and 9 clocks & Start-cond.) that is described in the attached file?

(2)

If the above is yes, could you show me how NT5T2111 acts when the clocks will short than 9 (eg. 8 clocks)?

(3)

After reading Chapter 9.3 of NT3H2111_2211 Datasheet(Rev.3.2), my customer believes that NT3H2111 will be reset every time Start conditions including repeated start are occurred when a condition of NFCS_I2C_RST_ON_OFF is set.

Is it true?

(4)

Do you have any description about a behavior of a condition NFCS_I2C_ON_OFF is cleared?

Best Regards, Shimura

[masafumishimura]

Hello

I think that the above specification is not official, but it is commonly adopted in general.
Would anyone please support above question?

Best Regards, Shimura

[estephania_mart]

Dear Masafumi Shimura, 

1.) and 2.) NTAG I²C plus (NT3H2111) does not support I2C soft reset as described above. It has its own form as described in Datasheet, page 39, chapter "9.3 I²C soft reset and NFC silence feature". 

3.) Yes, the drawback is that if NFCS_I2C_RST_ON_OFF is set, every "repeated start condition" on I²C bus, will reset NTAG's I²C subsystem.

4.) Everything available is written in that chapter. No additional functionality - i2c reset is implemented.

Best Regards, 

Estephania