How to drive ATX_C(RTS) pin high in PN7462

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How to drive ATX_C(RTS) pin high in PN7462

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Contributor III

Hi,

I want to use hardware flow control in HSUART of PN7462. But as turns out on when the end of the buffer occurs on RX buffer RTS pin does not desserts (0 to 1). This pin is on ATX_C on PN7462. Can I control  this pin manually and achieve flow hardware flow control manually

Thanks in advance. 

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8 Replies

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NXP TechSupport
NXP TechSupport

Hi @jayeshj ,

 

Actually there is no need to control this pin manually, the hardware controls it after this pin is enabled, the firmware just have to make sure the RX buffers are correctly configured, or disabled, before enabling the RTS pad.

 

Hope that makes sense,

 

Have a great day,
Kan


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Contributor III

Thanks, @Kan_Li for the response.

I have configured the Rx buffer 0 at 50 bytes. Now if the stream of 100bytes comes from PC and hardware flow control is enabled, Rx callback called after 100bytes are completely sent out by PC. And after that RTS changes to high in that way hardware flow control is useable here. Without manually controlling this pin I don't think the RTS pin quite matches the hardware flow control requirement.

So if possible to control the RTS pin manually I  may be able to handle stream larger than the buffer size by water level interrupt and manual control of RTS.

Regards Jayesh

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NXP TechSupport
NXP TechSupport

Hi @jayeshj ,

 

Is your application built based on the NFC reader library? Is it possible to share part of your code especially regarding the UART receiving ? We may try to reproduce your issue here.

 

Thanks for your patience!

 

Best Regards,

Kan

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Contributor III

@Kan_Li Thanks for the response

I am attaching HIF firmware. I have been able to achieve manual RTS functionality using GPIO_8 but the same functionality I want to achieve using ATX_C(HSUART_RTS ) pin as hardware is already designed.

 Let me know in case you need more information.

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NXP TechSupport
NXP TechSupport

Hi @jayeshj ,

 

Thanks for the information! I just checked with the expert regarding your issue, please kindly refer to the following for details.

 

This is not really a issue but expected behaviour. Please see UM10858 PN7462 family HW user manual [14.3.3.8 RTS/CTS flow control]: 

At the end of the frame reception, the buffer becomes unavailable and the RTS changes to 1 if no other buffer is available, until firmware programs a new buffer.

RTS only will toggle by receiving a EOF. If the RxBuffer is smaller as the receiving frame a buffer overflow interrupt will be generated and data >rxBufferSize will be lost. RTS will be asserted after the frame ended (reception of EOF).

This behaviour cannot be changed. 

Best would be to set the rx buffer size bigger as the expected maximum frame size. Multipe rx buffers can be used to operate in a parallel way. 

 

Hope that makes sense,

 

Have a great day,
Kan


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Contributor III

Thanks, @Kan_Li  for the response.

Thanks for the confirmation. I know that it is expected behavior. So now the question is there any chance I can toggle the ATX_C pin manually as shown in the datasheet. I am attaching screenshots for the same.

As per UM10858,  HSUART RTS (ATX_C) output driver can be enabled using a bit ATX_C_EN_OUT  of register PCR_PAD_ATX_C_REG.  I have tried setting high bit  PADOUT_ATX_C of register PCR_PADOUT_REG but the RTS pin does not set to 1.  Here is a screenshot from UM10858 for your reference. Am I missing something?

Regards Jayesh.

 
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NXP TechSupport
NXP TechSupport

Hi @jayeshj ,

 

How did you set up the bits of ATX_C_PUPD? 

 

Best Regards,

Kan

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Contributor III

@Kan_Li 

I am trying to set up bits of ATX_C_PUPD as per below

//Enable ATX_C (RTS) pin output driver and Set output to 1

PH_REG_SET_BIT( PCR_PAD_ATX_C_REG , ATX_C_EN_OUT );
PH_REG_SET_BIT( PCR_PADOUT_REG , PADOUT_ATX_C );

Regards Jayesh.

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