How to configure for Pass Through in NTAG I2C 1K Memory

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How to configure for Pass Through in NTAG I2C 1K Memory

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Contributor IV

Hi Sir / Madam,

I am developing microcontroller firmware to communicate to outside world through NTAG NFC (Reference: NT3H1101 / NT3H1201).  I am using NTAG I2C 1k memory, and have problem understand and configure for pass-through mode (NC_REG, bit#6 - PTHRU_ON_OFF) in session register ( I2C block address : 0xFE) .

My question is as follows:

(1)  I am not able to write to Bit#6 in NC_REG, example 0x7F or 0x40.  But I can write to all other bits, for example writing 0x3F.  Please help.

(2) The SRAM inside device memory start at block address 0xF8, allocate 64 bytes.  If I have written 1b to Bit#1 (SRAM_MIRROR_ON_OFF) inside NC_REG, and then written 0x01 to SRAM_MIRROR_BLOCK register,  the device will copy all SRAM contents from SRAM (block address 0xF8)  to first block of User memory (Block address 0x01).  Then, both I2C interface can read back the SRAM content from block address 0x01, with and without Pass-Through configured.  And, RF interface can read out the content of SRAM from this mirror location (block address 0x01) through NFC tag, with Pass-Through configured.  Am I right ? Please help.

(3) I can read back the register I have just written when I read back only 1 byte at a time, following the I2C diagram in the datasheet (Page 37, Figure 17). But when I read it back in 7 bytes ( The last is not read) in one read, I am not able to get the contents of other registers (Register byte#1 to Byte#5).    I can only read back 0xFF for all these registers. The only 2 register can be read back are the first (NC_REG) and last (NS_REG) registers.  Please help.

Please let me know if you need any more information.

Please help.  Thank you for your advice.

Cheers,

KF Choong

1 Solution
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NXP Employee
NXP Employee

Hi KF Choong,

 

Some feedback about your questions:

 

1) As explained in your other thread, both interfaces need to be ON for the pass-through mode to be enabled.

 

2) The SRAM_MIRROR_BLOCK value must be interpreted in terms of 16-byte blocks. So if you are setting this value to 0x01, the SRAM contents will be mirrored in the pages 0x04 to 0x13 from the NFC perspective (16 pages x 4 bytes = 64 bytes).

 

3) Can you tell me the read sequence you are using (I2C frames)? Please notice that the registers can only be read one-by-one, not all in a single I2C transfer.

 

I hope this helps.

Let me know if you still have issues.

 

Regards!

Jorge Gonzalez

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9 Replies
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Contributor I

Dear all,

i'm working with the NTAG 2K chip in passthrough mode without problems. However I have a doubt. In my application the passthrough in intensively used in both directions, so that I have to switch the" flags" I2C_TO_RF and RF_TO_I2C in a continous way during the day. Are these "flags" in SRAM of in EEPROM? If these flags are not mirrored in SRAM I suppose I have only 50.000 cycles of bi-directional communications before demaging the memory of the chip. Is it right?

Thank you.

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Contributor IV

Hi Jorge_Gonzalez,

I am trying to change the bit#6 (NS_REG) = 1b, but not able to change, the read back is always 0b.

I have done this in 4 condition :

(1) I2C To RF is Pass Through direction (PTHRU_DIR bit in NC_REG Register) is configure as  0b.

(2) RF To I2C is Pass Through direction (PTHRU_DIR bit in NC_REG Register) is configure as  1b. 

(3) I2C_LOCK Bit, I2C To RF is Pass Through direction (PTHRU_DIR bit in NC_REG Register) is configure as  0b,

     I2C_LOCKED Bit in NS_REG is configure as 1b.  

(4) I2C_LOCK Bit, RF To I2C is Pass Through direction (PTHRU_DIR bit in NC_REG Register) is configure as  1b,

     I2C_LOCKED Bit in NS_REG is configure as 1b.  

The read back are :

Register inside Session register Before 0xF8 is readI2C To RFRF To I2CI2C_LOCK Bit, I2C To RFI2C_LOCK Bit, RF To I2C
Nc_Reg'V' (0x56)'W' (0x57)'V' (0x56)'W' (0x57)
Last_Ndef_Block'\0' (0x00)'\0' (0x00)'\0' (0x00)'\0' (0x00)
Sram_Mirror_Block'.' (0x01)'.' (0x01)'.' (0x01)'.' (0x01)
Wdt_Ls'H' (0x48)'H' (0x48)'H' (0x48)'H' (0x48)
Wdt_Ms'\b' (0x08)'\b' (0x08)'\b' (0x08)'\b' (0x08)
I2c_Clock_Str'.' (0x01)'.' (0x01)'.' (0x01)'.' (0x01)
Ns_Reg')' (0x29)'!' (0x21)')' (0x29)'!' (0x21)

The I2C_LOCKED Bit in NS_REG is always 0b, although I write 1b to it.  Please advice.

Thank you.

Cheers,

KF Choong

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27 Views
NXP Employee
NXP Employee

Hi KF Choong,

 

Some feedback about your questions:

 

1) As explained in your other thread, both interfaces need to be ON for the pass-through mode to be enabled.

 

2) The SRAM_MIRROR_BLOCK value must be interpreted in terms of 16-byte blocks. So if you are setting this value to 0x01, the SRAM contents will be mirrored in the pages 0x04 to 0x13 from the NFC perspective (16 pages x 4 bytes = 64 bytes).

 

3) Can you tell me the read sequence you are using (I2C frames)? Please notice that the registers can only be read one-by-one, not all in a single I2C transfer.

 

I hope this helps.

Let me know if you still have issues.

 

Regards!

Jorge Gonzalez

View solution in original post

26 Views
Contributor IV

Hi Jorge_Gonzalez,

Millions thanks for your reply.  Your reply has help me tremendously.

Now I am able to configure for Pass Through after apply RF wave at RF Interface side.  I do this by constantly tagging it with a hand phone NFC, through NXP Tag info apps. 

However, I am not sure if SRAM is enabled in actual although the Bits (NC_REG register,  Bit#1 - SRAM_MIRROR_ON_OFF = 1b.  SRAM_MIRROR_BLOCK register, Bit#0 to #7 is 0x01) can be configured and the read back from session registers are correct.  Therefore, with the RF wave on, and after done all the configuration (PTHRU_ON_OFF = 1b,  SRAM_MIRROR_ON_OFF = 1b and SRAM_MIRROR_BLOCK = 0x01), I try to write to SRAM from I2C interface (Addr 0xF8 to 0xFB), then read back the mirrored data from I2C interface (Addr 0x01).  This has failed.  I am not able to read any memory from I2C interface.  After check some bits (NS_REG register : SRAM_I2C_READY = 0b, SRAM_RF_READY = 1b, RF_FIELD_PRESENT = 1b), I get to know that probably this failure is caused by the memory is lock to RF interface.  I have try to off the RF wave and try to access, It successful but Pass through is OFF.  By this way, the read back from address 0x01 is not the data which is mirrored fro SRAM.  May I know how can I check this ?  I would like to write to enable pass through, write SRAM(0x78) from I2C interface, then read back mirrored data from mirror block (0x01) by I2C interface, to confirm the data is successfully written and mirrored.  Please help me on this.  lese help me on this.

Yes, I follow your suggestion to read the memory in block size (16 bytes per block) by I2C interface.  I also read the register byte by byte, NOT 16 bytes in one time. The sequence I use to read the register is :  start -> nfc address and write command -> memory address- > Register address -> Stop,  then start -> nfc address and read command -> register data from nfc -> stop.  This method is proven successful and correct.

Please advice soon.

Thank you for your help.

Cheers,

KF Choong

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NXP Employee
NXP Employee

Hi KF Choon,

The SRAM Mirror and Pass-through modes cannot be combined, either use one or the other depending on your requirements.

Also, the SRAM memory is mirrored in EEPROM space for access from the NFC interface, not from the I2C interface. If you want to read the SRAM contents from I2C side you can simply read it from its original location (pages 0xF8 to 0xFB).

I hope this clarifies.

Regards!

Jorge Gonzalez

26 Views
Contributor IV

Hi Jorge Gonzalez,

Millions thanks for your reply.

May I ask what do you mean by " The SRAM Mirror and Pass-through modes cannot be combined, either use one or the other depending on your requirements."  ?  Isn't that If I want to configure for PASS THROUGH, I need to enable SRAM ?  If SRAM is not enabled, may I know how another NFC device will read the mirror data from the host NFC device ?  Don't I need to done correctly all the configuration before start the operation ( host_A NFC write to SRAM, host_B NFC read from host_A mirrored SRAM, then host_B NFC write to SRAM, host_A NFC read from host_B mirrored SRAM )

In my latest post, I am not able to read the SRAM content (Block Addr 0xF8) from I2C interface with all these configuration (Enable pass through, enable sram, and with sram mirror address configured).  Please advice soon.

Thank you for your advice.

Cheers,

KF Choong

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26 Views
Contributor IV

Hi Jorge Gonzalez,

Does "The SRAM Mirror and Pass-through modes cannot be combined, either use one or the other depending on your requirements" means the following :

(1) I need to OFF the Pass Through first, then,

(2) write to SRAM from I2C interface, then mirror it to block 0x01, then,

(3) Then OFF the SRAM mirror mode, apply RF wave, and then ON the Pass Through mode,

(4) Then, used another NFC device to retrieve the mirrored data from address page 0x04 (or Block 0x01 in I2C perspective)

Please advice soon.

Thank you.

Cheers,

KF Choong

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Contributor IV

Hi Jorge Gonzalez,

Millions Thanks to you again.

I think I have mirror the SRAM data to its mirror position (Page 0x04 from NFC device or block 0x01 from I2C perspective) correctly.  This is because, by using hand phone, I am able to read back the same data I wrote to the SRAM through I2C.   The procedure I have done is the following, with the absence of RF wave :

(1)  Set SRAM Mirror location address

(2) Enable SRAM Mirror Mode

(3) Write to SRAM (Block Address 0x78)

(4) Use Apps InfoTag to read the data.  The data appear correctly in page 0x04.

Thank you Jorge Gonzalez.

Cheers,

KF Choong

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Contributor IV

Hi Sir/ Madam,

I have done the following trials, but still, I am not able to write to the Pass-Through bit.

Please see attached excel file.

Write sequence               
LAST_NDEF_BLOCK0x000xFF0x37'ÿ' (0xFF)0xFF'ÿ' (0xFF)'ÿ' (0xFF)'ÿ' (0xFF)'ÿ' (0xFF)'\0' (0x00)'\0' (0x00)'\0' (0x00)'\0' (0x00)'\0' (0x00)'\0' (0x00)
SRAM_MIRROR_BLOCK0x000xFF0x01'ÿ' (0xFF)0xF8'ÿ' (0xFF)'ÿ' (0xFF)'ÿ' (0xFF)'ÿ' (0xFF)'ø' (0xF8)'ø' (0xF8)'ø' (0xF8)'ø' (0xF8)'ø' (0xF8)'ø' (0xF8)
WDT_LS0x000xFF0x48'H' (0x48)0x48'H' (0x48)'ÿ' (0xFF)'ÿ' (0xFF)'ÿ' (0xFF)'H' (0x48)'H' (0x48)'H' (0x48)'H' (0x48)'H' (0x48)'H' (0x48)
WDT_MS0x000xFF0xFF'\b' (0x08)0x08'\b' (0x08)'ÿ' (0xFF)'ÿ' (0xFF)'ÿ' (0xFF)'\b' (0x08)'\b' (0x08)'\b' (0x08)'\b' (0x08)'\b' (0x08)'\b' (0x08)
I2C_CLOCK_STR0x000xFF0x01'.' (0x01)0x01'.' (0x01)'.' (0x01)'.' (0x01)'.' (0x01)'.' (0x01)'.' (0x01)'.' (0x01)'.' (0x01)'.' (0x01)'.' (0x01)
NS_REG0x000xFF0x40'\0' (0x00)0x00'\0' (0x00)'@' (0x40)'@' (0x40)'@' (0x40)'\0' (0x00)'\0' (0x00)'\0' (0x00)'\0' (0x00)'\0' (0x00)'\0' (0x00)
NC_REG0x400x400x400x400x400x400x400x400x400x400x400x400x400x400x40
 Write Bit#6 FailWrite Bit#6 FailWrite Bit#6 FailWrite Bit#6 FailWrite Bit#6 FailWrite Bit#6 FailWrite Bit#6 FailWrite Bit#6 FailWrite Bit#6 FailWrite Bit#6 FailWrite Bit#6 FailWrite Bit#6 FailWrite Bit#6 FailWrite Bit#6 FailWrite Bit#6 Fail

Please advice soon.

Thank you.

Cheers,

KF Choong

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