Digital clock signal on XTAL1-pin of PN7462

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Digital clock signal on XTAL1-pin of PN7462

Contributor III


I am developing a board using a PN7462 controlled by a SoC. This SoC does have several free-to-use PLLs within in. Therefore we want to use these PLL to clock the PN7462 with a 27.12MHz 3.3V TTL signal instead of an crystal.


However, I am a little bit confused by the spec in the datasheet. Table 55 of the datasheet states that the maximum input pp voltage may lie between 200mV and 1.65V (section Input clock characteristics on XTAL1 when using PLL). The "analogue" signal may lie between 0V and 1.8V (Vdd) as stated by the section XTAL pin characteristics XTAL PLL input. It seems that "every" middle-voltage is allowed. No threshold voltage is been given as a digital input signal's high or low level.


Therefore I suppose that the PN7462 may not be clocked using, e.g., a 1.8V powered 74LVC04 gate, as the pp Vin would be 1.8V what is well beyond the stated 1.65V. Is that correct?

To level-convert the 3.3V TTL output signal accordingly I would use a voltage divider having 8.2k and 1.5k. Since the PN7462 has (typically) a 2pF input capacitance a charge curve can be seen with an amplitude of approx. 500mVpp, what is larger than the required 200mVpp. Needless to say, that the resulting curve isn't digital anymore (although the signal of a crystal is also sinusoidal). Is it safe to clock the PN7462 this way?


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NXP Employee
NXP Employee



you can clock it this bay but it will lead to reduced receiver performance. How much it will reduce needs to be checked in the setup with the uC. if the drop is nothing which could be compensated by margin on the reception and receiverperformance.



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