Hi Fabian,
yes, the default framesize defined in ISO 14443 is 256bytes. But ISO 14443 also defines the value of FSDI, which is used to configure larger framesizes (512byte, 1024byte, 2048byte) on the reader.
What I am trying to achieve here is to set this FSDI to 0xB, which means the max receive framesize is 2048bytes (in one frame, without chaining).
I have allocated the required buffers and adapted the memory management accordingly.
The only part of this operation that is failing the setting the buffer size in the hardware.
I have found that there is a register defined at address 0x40004020UL (CLIF_RX_BUFFER_REG).
It is not possible to read or write this register directly with PH_REG_GET/PH_REG_SET.
Can you confirm or deny that this is the register that is addressed via the config option PHHAL_RF_CONFIG_RX_MAX_LENGTH?
I am using the NxpNfcRdLib v05.19.00
In PN7462AU/phCommon/inc/PN7462AU/PN7462AU_clif.h I see:
#define CLIF_RX_BUFFER_REG (0x40004020UL) /**< rw*/
#define CLIF_RX_BUFFER_REG_RX_BUFFER_LENGTH_MASK (0x007F0000UL) /**< rw - Defines the length of the Rx buffer (in data words). */
#define CLIF_RX_BUFFER_REG_RX_BUFFER_LENGTH_POS (16UL)
Judging from the MASK, the largest value that can be set here is 0x7F (127 in decimal), and the comment in the same line states that this value is given in data words. As one data word is 4 bytes, we can deduce that the maximum value we can set here is 127*4=508
Can you confirm this?
Thanks and best regards,
lram